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Burroughs 

B6500 

Information Processing Systems 

REFERENCE MANUAL 



Bu.rrou.glis 

B 6500 
INFORMATION PROCESSING SYSTEMS 

REFERENCE MANUAL 



© 



Burroughs Corporation 

Detroit, Michigan 48232 



$5.00 



Printed in U.S. America 



9-69 



1043676 



COPYRIGHT® 1969 BURROUGHS CORPORATION 

The information contained herein is subject to change 

without notice. Revisions may be issued to advise of 

such changes and/or additions. 



Correspondence regarding this document should be forwarded using the Remarks Form at 
the back of the manual, or may be addressed directly to Systems Documentation, Sales 
Technical Services, Burroughs Corporation, 6071 Second Avenue, Detroit, Michigan 48232. 



TABLE OF CONTENTS 
SECTION TITLE PAGE 

INTRODUCTION • • xxvii 

1 SYSTEMS DESCRIPTION 1-1 

General 1-1 

Description of Units 1-1 

System Options and Requirements 1-5 

Auxiliary Cabinet 1-6 

System Power 1-6 

Peripheral Control Cabinet 1-8 

System Organization 1-9 

Master Control Program 1-9 

Clocks 1-9 

Processor 1-12 

Processor States 1-12 

Control State 1-12 

Normal State 1-12 

Features 1-13 

Interrupt System 1-13 

Interrupt Handling 1-14- 

Operator Dependent Processor Interrupts . . . 1-15 
Operator-Independent Processor Interrupts . . 1-15 

External Interrupts 1-16 

Main Memory 1-16 

Memory Words 1-17 

Memory Cycle Times 1-17 

Second Level Memory 1-17 

Input/Output Multiplexor . ♦ * 1-17 

Multiplexor Configuration 1-17 

Data Switching Channels 1-18 

Peripheral Controls 1-18 

System Expansion 1-18 

Peripheral Control Bus 1-19 

Processor Initiated i/O Operations 1-21 



in 



TABLE OF CONTENTS (cont) 
SECTION TITLE PAGE 

1 (cont) Peripheral Control. , 1-21 

Data Communications Processor 1-21 

Data Communications Adapters 1-22 

Real Time Adapter 1-24 

2 DATA REPRESENTATION 2-1 

General 2-1 

Internal Character Codes 2-1 

Number Bases 2-2 

Hexadecimal and Octal Notation 2-2 

Number Conversion 2-4 

Coded to Decimal Conversion 2-4 

Decimal To Coded 2-4 

Decimal and Hexadecimal Table Conversion . . 2-5 

Hexadecimal to Decimal 2-5 

Decimal to Hexadecimal 2-5 

Order of Magnitude 2-7 

Data Types and Physical Layout 2-8 

Character Type 2-8 

Operands 2-9 

Mantissa Field 2-10 

Logical Operands 2-12 

Operators 2-12 

3 STACK AND POLISH NOTATION. 3-1 

The Stack 3_1 

General „ 3-1 

Base and Limit of Stack 3-2 

Bi-Directional Data Flow In the Stack. . . . 3-2 

Double-Precision Stack Operation 3-2 

Data Addressing ...» 3-3 

Data Descriptor. . 3-3 



IV 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

3 (cont) Presence Bit 3-4 

Index Bit 3-4 

Invalid Index. 3-4 

Valid Index 3-4 

Read-Only Bit 3-5 

Copy Bit 3-5 

Polish Notation 3-5 

General 3-5 

Rules for Generation of Polish String .... 3-7 

Polish String 3-8 

Rules for Evaluating a Polish String 3-8 

Simple Stack Operation 3-9 

Program Structure In Memory 3-l4 

Memory Area Allocation 3-l4 

Stack-History and Addressing-Environment 

Lists 3-16 

Mark Stack Control Word Linkage 3-l6 

Stack Deletion 3-16 

Relative-Addressing 3-18 

Base of Addressing-Level Segment. . . . 3-20 

Absolute Address Conversion 3-20 

Multiple Variables With Common 

Address Couples 3-20 

Address Environment Defined 3-21 

Mark Stack Control Word Linkage .... 3-21 

Stack History Summary 3-21 

Multiple Stacks and Re-Entrant Code 3-22 

Level Definition 3-22 

Re-Entrance 3-22 

Job-Splitting 3-22 

Stack Descriptor . . . . 4 3-23 

Stack Vector Descriptor. 3-24 

Presence Bit Interrupt 3-24 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

4 MAJOR REGISTERS AND CONTROL PANELS. . ., 4-1 

General , 4-1 

Panel A , 4-1 

A Register 4-1 

B Register 4-1 

C Register 4-2 

X Register . 4-2 

Y Register 4-2 

P Register 4-2 

Panel B 4-2 

Row A 4-2 

Row B . 4-2 

Row C 4-5 

Family A 4-5 

Arithmetic Control 4-5 

Row D 4-6 

Family B 4-6 

Family C 4-6 

Row E 4-6 

Family D 4-6 

Family E 4-7 

Row F 4-7 

Row G 4-8 

Interrupt Controller 4-8 

Stack Controller 4-9 

Memory Controller 4-9 

Row H 4-10 

Program Controller 4-10 

Transfer Controller 4-11 

General Maintenance Control 4-11 

Power Controls 4-12 

General Clear and Halt-Load Function. . . . 4-12 

Processor Register Clear 4-14 

vi 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

4 (cont) Multiplexor Register Clear 4-l4 

MDL Register Clear 4-l4 

MDL Control Switches 4-l4 

Display Select Switches 4-l4 

Clock Controls 4-15 

Single Pulse Switch 4-15 

Pulse Train Switch 4-15 

Indicators BO , Bl , B2 4-15 

MDTR/Normal Switch 4-15 

FF Reset Switch 4-l6 

Halt Load and Load Select Switches 4-l6 

Processor Maintenance Controls (Panel E) . . . 4-l6 

Start Switch 4-l6 

Conditional Halt Switch 4-17 

Stop Switches 4-17 

SECL Switch 4-17 

INT-I Switch 4-17 

EXT-I Switch 4-17 

Normal/Control State Switches ....... 4-18 

Parity Switch 4-18 

Unit Clear Switch 4-18 

Local/Remote Switch 4-18 

ADJ (0,0) Switch 4-18 

Read IC Switch 4-18 

Read IC Operation 4-19 

Write IC Switch 4-19 

Write IC 4-19 

Read Proc Reg Switches 4-20 

Multiplexor Registers and Flip Flops 4-22 

Row B 4-22 

Row C 4-23 

Row D 4-23 

Row E 4-23 

vii 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

4 (cont) Row F 4-24 

Row G 4-24 

Row H 4-26 

MPX Maintenance Control Panel 4-26 

Write SPM 4-27 

Read SPM 4-27 

Write Main Memory 4-28 

Read 1 Main Memory 4-28 

Executing I/O Descriptors 4-29 

Single Cycle 4-29 

Recycle 4-30 

Logic Card Testing 4-32 

Operators Control Console 4-32 

Operator Panel 4-32 

Power On (Switch Indicator, White) .... 4-32 

Power Off (Switch, Brown). 4-32 

Halt Switch ( Switch/indicator , Red). . . . 4-32 

Running (indicator, Yellow). . . 4-33 

Load Select ( Switch/indicator , Yellow) . . 4-33 

Load (Switch, Brown) 4-33 

Card Load Operation 4-33 

Disk Load Operation 4-34 

Visual Message Control Center ........ 4-34 

Keyboard Control Keys , . . . . 4-36 

Memory Tester 4-40 

Non-Test 4-4l 

Test 4-41 

5 SYSTEM CONCEPT 5_ x 

General 5-1 

Processor 5-1 

Operator Families 5-1. 



VI 11 



TABLE OP CONTENTS (cont) 

SECTION TITLE PAGE 

5 (cont) Program Controller 5-2 

Transfer Controller 5-3 

Stack Registers 5-3 

Internal Data Transfer Section .... 5-3 

Mask and Steering 5-5 

Mask and Steering Example 5-6 

Arithmetic Controller 5-6 

High Speed Adder 5-6 

Interrupt Controller 5-8 

Operator Dependent Interrupts 5-9 

Memory Protect 5-10 

Invalid Operand 5-H 

Divide by Zero 5-11 

Exponent Overflow and Underflow . . 5-H 

Invalid Index 5-12 

Integer Overflow 5-13 

Bottom of Stack 5-13 

Presence Bit 5-13 

Data-Dependent Presence Bit. . . 5-1^ 

Procedure-Dependent Presence 

Bit 5-1^ 

Program Restart 5-15 

Segmented Array 5-15 

Programed Operator 5-15 

Operator Independent Interrupts. . . . 5-17 

External Interrupts 5-17 

Processor to Processor 5-18 

Interval Timer 5-18 

Stack Overflow 5-18 

Multiplexor Interrupts 5-19 

Scan Bus Control 5-19 

Priority Handling Example 5-19 



xx 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

5 (cont) Priority Handling With IIHF Set. . . 5-20 

I/O Finished Data Communications . . 5-20 

General Control Adapter 5-21 

External MPX 5-21 

Alarm Interrupts 5-21 

Loop 5-22 

Memory Parity 5-22 

MPX Parity 5-22 

Invalid Address ^-2h 

Stack Underflow 5-24 

Invalid Program Word 5-24 

Interrupt Handling 5-25 

String Operator Controller 5-25 

Control State/Normal State 5-27 

Input/Output Multiplexor 5-29 

Scan Bus 5-29 

Command Data Register 5-29 

Scratch Pad Memory 5-29 

Tag Register 5-31 

Memory Exchange 5-31 

Interrupt Network . 5-31 

Time of Day Register, 5-31 

Channel Assignment Control 5-31 

Character Translator 5-31 

Peripheral Control Interface 5-33 

Data Communications Interface 5-33 

System Clock Control and MDL Processor. . . . 5-33 

System Clock 5-33 

Maintenance Diagnostic Processor 5-34 

Display Mode 5-34 

Diagnose Mode 5-34 

Detect Mode 5-34 



x 



TABLE OF CONTENTS (cont) 
SECTION TITLE PAGE 

5 (cont) Information Flow From Card Reader To 

Main Memory 5-35 

Alpha Card Read 5-35 

Binary Card Read 5-35 

EBCDIC Card Read 5-36 

Memory and MPX Controller 5-36 

Memory Bus 5-39 

Scan Bus 5-^0 

Address Adder 5-^0 

Integrated Chip Memory 5-^+0 

Main Memory 5-^-1 

Organization 5-^1 

Memory Protection 5-^-2 

Cabinet Configuration 5-^3 

Interface 5-^3 

Priority 5-^3 

Memory Registers. 5-^+6 

Memory Addressing 5-^6 

Memory Interlacing 5-^6 

Memory Testing 5-^7 

Stack Controller 5-^+7 

6 PROGRAM OPERATORS 6-1 

General 6-1 

Syllable Addressing and Syllable 

Identification . 6-1 

Syllable Format and Addressing 6-1 

P and T Registers 6-1 

Operation Types 6-2 

Name Call 6-3 

Value Call 6-3 

Operators 6-3 

Word Data Descriptor 6-5 

String Descriptor 6-7 

xi 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

6 (cont) Segment Descriptor 6-9 

Mark Stack Control Word 6-10 

Program Control Word 6-11 

Return Control Word 6-12 

Indirect Reference Word 6-lk 

Stuffed Indirect Reference Word 6-lk 

Step Index Word 6-16 

7 PRIMARY MODE OPERATORS 7_! 

General 7-1 

Arithmetic Operators 7-1 

Add (ADD) 80 7_ 2 

Subtract (SUBT) 81 7_3 

Multiply (MULT) 82 7.3 

Extended Multiply (MULX) 8P 7_3 

Divide (DIVD) 83 . 7.4 

Integer Divide (iDIV) 8k 7_4 

Remainder Divide (RDIV) 85 7_5 

Integerize, Truncated (NTIA) 86 7-5 

Integerize, Rounded (NTGR) 87 7_6 

Type-Transfer Operators 1-6 

Set to Single-Precision, Truncated 

(SNGT) CC 7_6 

Set to Single-Precision, Rounded 

(SNGL) CD 7_7 

Set to Double-Precision (XTND) CE 7-7 

Logical Operators 1-8 

Logical And (LAND) 90 7_8 

Logical Or (LOR) 91 7_8 

Logical Negate (LNOT) 92 7_8 

Logical Equivalence (LEQV) 93. . ., 7-8 

Relational Operators , 1-9 

Logical Equal (SAME) 9k. . 7.9 

Greater Than (GRTR) 8A . . 7_9 

xii 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

7 (cont) Greater Than or Equal (GREQ) 89 7-9 

Equal (EQUL) 8C 7-9 

Less Than or Equal (LSEQ) 8B 7-9 

Less Than (LESS) 88 7-10 

Not Equal (NEGL) 8D 7-10 

Branch Operators. , 7-10 

Branch False (BRFL) AO 7-10 

Branch True (BRTR) Al 7-10 

Branch Unconditional (BRUN) A2 7-10 

Dynamic Branch False (DBFL) A8 7-H 

Dynamic Branch True (DBTR) A9 7-H 

Dynamic Branch Unconditional (DBUN) AA . . . 7-11 

Step and Branch (STBR) Ak 7-12 

Universal Operators 7-12 

No Operation (NOOP) FE 7-12 

Conditional Halt (HALT) DF 7-12 

Invalid Operator (NVLD) FF 7-12 

Store Operators 7-12 

Store Destructive (STOD) B8 7-13 

Store Non-Destructive (STON) B9 7-13 

Overwrite Destructive (OVRD) BA 7-13 

Overwrite Non-Destructive (OVRN) BB 7-13 

Stack Operators 7-13 

Exchange (EXCH) B6 7-13 

Delete Top Of Stack (DLET) B5 7-1^ 

Duplicate Top Of Stack (DUPL) B7 7-1^ 

Push Down Stack Registers (PUSH) Bk 7-1^ 

Literal Call Operators 7-1^- 

Lit Call Zero (ZERO) BO 7-1^ 

Lit Call One (ONE) Bl 7-1^ 

Lit Call 8 Bits (LT8) B2 7-l4 

Lit Call 16 Bits (LTl6) B3 7-1^ 

Lit Call 48 Bits (LT48) BE 7-1^ 

xiii 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

7 (cont) Make Program Control Word (MPCW ) BF 7-15 

Index and Load Operators? 7-15 

Index (INDX) A6 7-15 

Index and Load Name (NXLN) A5 7-1 6 

Index and Load Value (NXLV) AD 7-16 

Load (LOAD) BD .. 7-l6 

Scale Operators 7-17 

Scale Left (SCLF) CO 7-17 

Dynamic Scale Left (DSLF) CI 7-17 

Scale Right Save (SCRS) Ck 7-17 

Dynamic Scale Right Save (DSRS) C5 7-18 

Scale Right Truncate (SCRT) C2 7-18 

Dynamic Scale Right Truncate (DSRT) C3 . . . . 7-18 

Scale Right Final (SCRF) C6 7-18 

Dynamic Scale Right Final (DSRF) C7 7-18 

Scale Right Rounded (SCRR) C8 7-18 

Dynamic Scale Right Round (DSRR) C9 7-19 

Bit Operators 7-19 

Bit Set (BSET) 96 7-19 

Dynamic Bit Set (DBST) 97 7-19 

Bit Reset (BRST) 9E 7-19 

Dynamic Bit Reset (DBRS) 9F 7-20 

Change Sign Bit (CHSN) 8E 7-20 

Transfer Operators , . 7-20 

Field Transfer (FLTR) 98 7-20 

Dynamic Field Transfer (DFTF) 99 7-21 

Field Isolate (iSOL) 9A 7-21 

Dynamic Field Isolate (DISO) 9B 7-21 

Field Insert (iNSR) 9C 7-22 

Dynamic Field Insert (DINS) 9D . . 7-22 

String Transfer Operators ...... 7-23 

Transfer Words, Destructive (TWSD) D3 7-23 

Transfer Words, Update (TWSU) DB . ., 7-23 

xiv 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

7 (cont) Transfer Words, Overwrite Destructive 

(TWOD) Bk 7-23 

Transfer Words , Overwrite Update (TWOU) DC . 7-23 

Transfer While Greater, Destructive 

(TGTD) E2. 7-24 

Transfer While Greater Update (TGTU) EA . . . 7-24 

Transfer While Greator or Equal , 

Destructive (TGED) El 7-25 

Transfer While Greater or Equal, Update 

(TGEW) E9 7-25 

Transfer While Equal, Destructive (TGED) Ek . 7-25 

Transfer While Equal, Update (TEGU) EC . . . 7-25 

Transfer While Less or Equal , 

Destructive (TLED) E3 7-25 

Transfer While Less or Equal, Update 
(TLEU) EB 7-25 

Transfer While Less, Destructive (TLSD) EO . 7-25 

Transfer While Less, Update (TLSU) E8 . . . . 7-26 
Transfer While Not Equal, Destructive 

(TNED) E5 7-26 

Transfer While Not Equal, Update (TNEU) ED . 7-26 

Transfer Unconditional, Destructive 
(TUND) E6 7-26 

Transfer Unconditional, Update (TUNU) EE . . 7-26 

String Isolate (SISO) D5 . . . 7-26 

Compare Operators 7-27 

Compare Characters Greater, Destructive 

(CGTD) F2 7-27 

Compare Characters Greater, Update 

(CGTU) FA 7-27 

Compare Characters Greater or Equal, 

Destructive (CGED) Fl 7-28 

Compare Characters Greater or Equal, 

Update (CGEU) F9 7-28 

Compare Characters Equal, Destructive 

(CEGD) F4 7-28 



xv 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

7 (cont) Compare Characters Equal, Update 

(CEGU) FC 7 _28 

Compare Characters Less or Equal, 

Destructive (CLED) F3 7-28 

Compare Characters Less or Equal, 

Update (CLEU) >B 7-28 

Compare Characters Less , Destructive 

(CLSD) FO 7 _28 

Compare Characters Less , Update 

(CLSU) F8. 7 _28 

Compare Characters Not Equal, Destructive 

(CNED) F5 7-29 

Compare Characters Not Equal, Update 

(CNEU) FD. . 7_29 

Edit Operators 7-29 

Table Enter Edit, Destructive (TEED) DO. . . 7-29 

Table Enter Edit, Update (TEEU) D8 7-30 

Execute Single Micro , Destructive 

(EXSD) D2 7-30 

Execute Single Micro, Update (EXSU) DA . . . 7-30 

Execute Single Micro, Single Pointer 

Update (EXPU) DD 7-30 

Pack Operators 7-30 

Pack, Destructive (PACD) Dl 7-30 

Pack, Update (PACU) D9 7-31 

Input Convert Operators 7-31 

Input Convert, destructive (iCVD) CA . . . . 7-31 

Input Convert, Update (iCVU) CB 7-32 

Read True False Flip Flop (RTFF) DE 7-32 

Set External Sign (SXSN) D6 7-32 

Read And Clear Overflow Flip Flop (ROFF) D7 . 7-32 

Subroutine Operators 7-32 

Value Call (VALC) 00 => 3F 7-32 

Name Call (NAMC) kO => 7F 7-33 



xv 1 



TABLE OF CONTENTS (cont) 
SECTION TITLE PAGE 

7 (cont) Exit Operator (EXIT) A3 7-36 

Return Operator (RETN) A7 . . . 7-36 

Enter Operator (ENTR) AB 7-36 

Evaluate (EVAL) AC 7-36 

Mark Stack Operator (MKST) AE 7-^0 

Stuff Environment (STFF) AE 7-40 

Insert Mark Stack Operator (iMKS) CF . . . . 7-40 

8 VARIANT MODE OPERATION AND OPERATORS 8-1 

General ... ....... 8-1 

Operators 8-1 

Set Two Singles to Double (JOIN) 95^2. . . . 8-1 

Set Double to Two Singles (SPLT) 95^3- • • . 8-1 

Idle Until Interrupt (IDLE) 95^ 8-2 

Set Interval Timer (SINT) 95^5 8-2 

Enable External Interrupts (EEXl) 95^6 . . . 8-2 

Disable External Interrupts (DEXl) 95^7- • • 8-2 

Scan Operators 8-2 

Read Time Of Day Clock 8-3 

Read General Control Adapter 8-k 

Read Result Descriptor 8-4 

Read Interrupt Mask 8-6 

Read Interrupt Register 8-7 

Read Interrupt Literal 8-8 

Interrogate Peripheral Status 8-9 

Interrogate Peripheral Unit Type 8-10 

Interrogate I/O Path 8-12 

Scan Out (SCNO) 95^B 8-13 

Set Time Of Day Clock 8-1^ 

Set General Control Adapter 8-l4 

Initiate i/O. (Control State Only) 8-15 

Read Processor Identification (WHOl) 95^E. . 8-17 



XV 11 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

8(cont) Interrupt Other Processor (HEYU) 95^F. . . . 8-17 

Occurs Index (OCRX) ' 9585 8-17 

Integerized, Rounded, Double-Precision 

(NTGD) 9587 8-19 

Leading One Test (L0G2) 958B 8-19 

Move To Stack (MVST) 95AF 8-19 

Set Tag Field (STAG) 95B4 8-20 

Read Tag Field (RTAG) 95B5 8-21 

Rotate Stack Up (RSUP) 95B6 8-21 

Rotate Stack Down (RSDN) 95B7 8-21 

Read Processor Register (RPRR) 95B8 8-22 

Set Processor Register (SPRR) 95B9 8-23 

Read With Lock (RDLK) 95BA 8-23 

Count Binary Ones (CBON) 95BB 8-23 

Load Transparent (LODT) 95BC 8-23 

Linked List Lookup (LLLU) 95BD 8-23 

Masked Search For Equal (SRCH) 95BE 8-2^ 

Unpack Absolute, Destructive (UABD) 95D1 . . 8-25 

Unpack Absolute, Update (UABU) 95D9 8-26 

Unpack Signed, Destructive (USND) 95DO . . . 8-26 

Unpack Signed, Update (USNU) 95D8 8-26 

Transfer While True, Destructive (TWTD) 

95D3 8-26 

Transfer While True, Update (TWTU) 95DB. . . 8-27 

Transfer While False, Destructive (TWFD) 

95D2 8-27 

Transfer While False, Update (TWFU) 95DA . . 8-27 

Translate (TRNS) 95D7 8-27 

Scan While Greater, Destructive (SGTD) 

95F2 8-28 

Scan While Greater, Update (SGTU) 95FA . . . 8-28 

Scan While Greater or Equal, 

Destructive (SGED) 95F1 8-29 

Scan While Greater or Equal, Update 

(SEGU) 95F9 8-29 

xviii 



TABLE OF CONTENTS (cont) 
SECTION TITLE PAGE 

8 (cont) Scan While Equal, Destructive 

(SEQD) 95F4. 8-29 

Scan While Equal, Update (SEQU) 95FC .... 8-29 

Scan While Less or Equal, Destructive 

(SLED) 95F3 8-29 

Scan While Less or Equal, Update 

(SLEU) 95PB 8-29 

Scan While Less , Destructive (SLSD) 

95FO 8-29 

Scan While Less, Update (SLSU) 95F8 8-29 

Scan While Not Equal, Destructive (SNED) 

95F5 8-30 

Scan While Not Equal, Update (SNEU) 95FD . . 8-30 

Scan While True, Destructive ( SWTD ) 95D5 . • 8-30 

Scan While True, Update (SWTU) 95DV 8-30 

Scan While False, Destructive (SWFD) 

95D4 8-30 

Scan While False, Update (SWFU) 95DC .... 8-30 

9 EDIT MODE OPERATION AND OPERATORS 9-1 

General 9-1 

Edit Mode Operators 9-1 

Move Characters (MCHR) D7 9-1 

Move Numeric Unconditional (MVNU) D6 .... 9-2 

Move With Insert (MINS) DO 9-2 

Move With Float (MFLT) Dl 9-3 

Skip Forward Source Characters (SFSC) D2 . . 9-3 

Skip Reverse Source Characters (SRSC) D3 . . 9-h 

Skip Forward Destination Characters ( SFDC ) 

DA 9-4 

Skip Reverse Destination Characters (SRDC) 

DB 9-4 

Reset Float (RSTF) D4 9-4 

End Float (ENDF) D5 9-h 

Insert Unconditional (iNSU) DC 9-4 

Insert Conditional (iNSC) DD 9-5 

xix 



TABLE OF CONTENTS (cont) 

SECTION TITLE PAGE 

9 (cont) Insert Display Sign (iNSG) D9 9-5 

Insert Overpunch (iNOP) D8 9-5 

End Edit (ENDE) DE 9-6 

10 INPUT/OUTPUT MULTIPLEXOR AND PERIPHERAL CONTROLS . 10-1 

General 10-1 

Operation 10-1 

Descriptor Formats 10-2 

Address Word 10-3 

Area Descriptor 10-3 

I/O Control Word 10-3 

Result Descriptor 10-4 

Peripheral Units and Associated Peripheral 

Controls 10-5 

Console 10-5 

Card Reader 10-7 

Card Punch 10-10 

Line Printers 10-12 

Magnetic Tape Subsystem 10-14 

Disk File Subsystem. 10-20 

Paper Tape 10-24 

11 B 6500 DATA COMMUNICATIONS SYSTEM 11-1 

General 11-1 

Data Communications Processor (D.C.P, ) 11-1 

Adapter Cluster 11-3 

Line Adapter 11-5 

APPENDIX A - OPERATORS, ALPHABETICAL LIST A-l 

APPENDIX B - OPERATORS , NUMERICAL LIST PRIMARY MODE B-l 

APPENDIX C - CONTROL WORD FORMATS C-l 

APPENDIX D - SCAN FUNCTION CODE WORDS D-l 

APPENDIX E - DATA REPRESENTATION E-l 

APPENDIX F - B 6500 EBCDIC/HEX CARD CODE F-l 

APPENDIX G - HEXADECIMAL -DECIMAL CONVERSION TABLE G-l 



xx 



LIST OF ILLUSTRATIONS 

FIGURE TITLE PAGE 

1-1 Auxiliary Cabinets 1-6 

1-2 B 6500 Power Supply 1_7 

1-3 Peripheral Control Cabinet 1-8 

1-4 B 65OO Schematic Diagram 1-11 

1-5 Possible Magnetic Tape Subsystem 1-19 

1-6 Possible Disk File Subsystem 1-20 

1-7 Input/Output Subsystem 1-20 

1-8 Organization of Data Communications Processor 

Remote Lines 1-22 

2-1 Basic Word Structure 2-1 

2-2 Number Base Graphic Characters 2-2 

2-3 Binary to Hexadecimal and Octal Conversion. . . . 2-3 

2-4 Relationship of Octal, Decimal and Hexadecimal 

Numbers ..... 2-3 

2-5 Hexadecimal and Octal To Decimal 2-4 

2-6 Decimal 1013 To Hexadecimal And Octal 2-5 

2-7 HEX and DEC Table Conversion 2-6 

2-8 Order of Magnitude Table 2-7 

2-9 (-4259) in 8, 6, and 4-Bit Code 2-8 

2-10 A Single-Precision Operand 2-10 

2-10 B Single-Precision Operand 2-11 

2-11 Double-Precision Operand 2-11 

2-12 Logical Operand 2-12 

3-1 Top of Stack and Stack Bounds Registers 3-1 

3-2 Polish Notation Flow Chart 3-6 

3-3 Stack Operation 3-11 

3-4 Object Program in Memory 3-15 

3-5 Stack History and Addressing Environment List . . 3-17 

3-6 Stack Cut-Back Operation on Procedure Exit. . . . 3-17 

3-7 D Registers Indicating Current Addressing 

Environment 3-18 



xxi 



LIST OF ILLUSTRATIONS (cont) 

FIGURE TITLE PAGE 

3-8 ALGOL Program With Lexicographical Structure 

Indicated 3-19 

3-9 Addressing Environment Tree of ALGOL 

Program 3-19 

3-10 Multiple Linked Stacks , 3-23 

4-1 Processor Display Panels 4-1 

4-2 Processor Display Panel. .... 4-3 

4-3 Processor/Multiplexor Display Panel 4-4 

4-4 Panel C General Controls 4-13 

4-5 Address Register 4-21 

4-6 Panel E . 4-22 

4-7 Panel B 4-25 

4-8 Panel D MPX Control Panel 4-31 

4-9 Operators Control Console 4-35 

4-10 Visual Message Control Center 4-36 

4-11 Keyboard Format 4-40 

4-12 Memory Tester 4-40 

4-13 Memory Tester 4-42 

5-1 B 6500 Processor Organization 5-2 

5-2 B 65OO Processor Block Diagram 5-4 

5-3 Internal Data Transfer Section 5-7 

5-4 Mask and Steering. . 5-8 

5-5 Arithmetic Control 5-9 

5-6 Presence Bit Interrupt 5-16 

5-7 B 6500 Scan Bus Priority Control 5-23 

5-8 Stack Format 5-26 

5-9 String Op Controller 5-28 

5-10 E Register Functions 5-28 

5-11 Multiplexor Block Diagram 5-30 

5-12 Command Data Register and Scratch Pad Memory . . . 5-32 

5-13 Data Information Flow 5-37 



xx 11 



LIST OF ILLUSTRATIONS (cont) 

FIGURE TITLE PAGE 

5-l4 Memory Controller Decoding 5-38 

5-15 Memory Organization 5-4l 

5-l6 Information Transmission 5-42 

5-17 B 6500 Memory Configuration 5-44 

5-18 Memory Module Selection 5-45 

5-19 Memory Registers 5-46 

5-20 Interlace Addressing. 5-47 

5-21 Hardware Stack Adjustment 5-^+8 

6-1 Program Word 6-1 

6-2 Program ¥ord , Syllable Addressing 6-2 

6-3 Syllable Decode Table 6-3 

6-4 Word Data Descriptor 6-5 

6-5 String Descriptor (Non-indexed) 6-7 

6-6 Byte/Word Index Field 6-8 

6-7 Segment Descriptor 6-9 

6-8 Mark Stack Control Word 6-10 

6-9 Program Control Word 6-11 

6-10 Return Control Word 6-12 

6-11 Stuffed Indirect Reference 6-l4 

6-12 Normal Indirect Reference Word 6-15 

6-13 Program Level Bit Assignment 6-l6 

6-l4 Step Index Word 6-16 

7-1 Flow of Value Call Operator 7-34 

7-2 Flow of Value Call Operator (cont) 7-35 

7-3 Flow of Exit Operator 7-37 

7-4 Flow of Return Operator 7-38 

7-5 Flow of Enter Operator 7-39 

7-6 Flow of Evaluate Operator 7-4l 

7-7 Flow of Stuff Environment Operator 7-42 



xxi 11 



LIST OF ILLUSTRATIONS (cont) 

FIGURE TITLE PAGE 

8-1 Read Time-Of-Day Code Word 8-2 

8-2 Time of Day Word 8-3 

8-3 Read General Control Adapter Code Word 8-4 

8-4 Read Result Descriptor Code Word 8-5 

8-5 Result Descriptor 8-5 

8-6 Read Interrupt Mask Code Word 8-6 

8-7 Interrupt Mask Word 8-6 

8-8 Read Interrupt Register Code Word 8-7 

8-9 Interrupt Register Word 8-7 

8-10 Read Interrupt Literal Code Word 8-8 

8-11 Interrupt Literal Word 8-9 

8-12 Interrogate Peripheral Status Code Word 8-9 

8-13 Status Vector Word 8-10 

8-14 Interrogate Peripheral Unit Type Code-Word. . . . 8-11 

8-15 Unit Type Code Word 8-11 

8-16 Interrogate i/O Path Code Word 8-12 

8-17 I/O Path Result Word 8-13 

8-18 Set Time Of Day Clock Code Word 8-l4 

8-19 Time Of Day Word. 8-l4 

8-20 Set General Control Adapter Code Word 8-15 

8-21 Initiate i/O Code Word. 8-15 

8-22 Area Descriptor 8-l6 

8-23 I/O Control Word. 8-16 

8-24 Index Control Word. 8-18 

8-25 Index Word 8-18 

8-26 Top of Stack Control Word (TSCW) 8-20 

8-27 Stack Rotation Up 8-21 

8-28 Stack Rotation Down 8-21 

10-1 Input/Output Subsystem 10-1 

10-2 i/O Descriptor Formats 10-2 

10-3 Result Descriptor Format 10-5 

10-4 Console Control Center 10-6 

xx iv 



LIST OF ILLUSTRATIONS (cont) 

FIGURE TITLE PAGE 

10-5 Single Line Control Result Descriptor 10-7 

10-6 Single Line Control I/O Control Word 10-7 

10-7 Card Reader 10-8 

10-8 Card Reader i/O Control Word 10-8 

10-9 Card Read Result Descriptor 10-9 

10-10 Card Punch 10-10 

10-11 Card Punch i/O Control Word 10-11 

10-12 Card Punch Result Descriptor 10-11 

10-13 Line Printer 10-12 

10-14 Line Printer i/O Control Word 10-13 

10-15 Line Printer Result Descriptor 10-13 

10-16 Free Standing Magnetic Tape Unit ........ 10-15 

10-17 Cluster Tape Unit 10-15 

10-18 Magnetic Tape Configuration 10-17 

10-19 I/O Control Word Magnetic Tape 10-18 

10-20 Magnetic Tape Result Descriptor 10-19 

10-21 Basic Disk File Subsystem 10-21 

10-22 Disk File Configurations 10-21 

10-23 Disk File i/O Control Word 10-23 

10-24 Disk File Result Descriptor 10-23 

10-25 B 9120 Paper Tape Reader 10-25 

10-26 B 9220 Paper Tape Punch 10-26 

10-27 Paper Tape i/O Control Word and Operations . . . 10-27 

10-28 Paper Tape Result Descriptor 10-28 

11-1 B 6500 System Configuration Including Data 

Communications 11-2 

11-2 DCP Block Diagram 11-4 

11-3 Adapter Cluster 11-6 



XXV 



LIST OF TABLES 

TABLE TITLE PAGE 

1-1 B 6500 Central Units Chart 1-2 

3-1 Evaluation of Polish String BC + 7 x A: = .... 3-9 

3-2 Description of Stack Operation 3-12 

6-1 Sub-Field Lengths 6-16 

10-1 F Field Codes 10-4 

10-2 Peripherals and Controls 10-6 

10-3 Available Magnetic Tape Subsystems 10-16 

10-4 Magnetic Tape Operations 10-18 

10-5 Disk File Subsystem Types 10-22 

11-1 Data Communications Terminal Compatibility. . . . 11-7 



xxvi 



INTRODUCTION 

The Burroughs B 65OO is a medium to large, high speed Information 
Processing System. Some features that are incorporated in this 
system include: 

a. Monolythic Circuitry. 

b. Memory expandable to 524,288 words. 

c. Memory Cycle Times of 1.2 microseconds or 600 nanoseconds. 

d. Peripheral configuration expandable to 256 units. 

e. Dual Input/Output Multiplexor permitting up to 20 simul- 
taneous Input/Output (i/o) operations. 

f . Data Communication Software for remote computing and file 
manipulation. 

g. Disk Pile storage over 36 billion bytes (8-bit characters) 

A unique hardware design, developed from years of successful ex- 
perience with the B 5000 series, has resulted in the parallel de- 
sign of the B 65OO hardware and software. Where traditionally hard- 
ware was designed prior to software development, parallel design 
assures that the hardware contains all necessary logic for effi- 
cient software packages, which in turn optimizes hardware capa- 
bilities. The B 65OO design affords a general "re-entrant" tech- 
nique which permits multiple users to share a common object program, 
In addition, the systems further expand the use of hardware stack 
organization used in the B 5500* For example, the Segment Diction- 
ary, a separate table for each program in the B 5500 , has been 
placed in the base of the program stack in the B 65OO. This part 
of the stack is used for multiple executions of the same program, 
thus implementing in the hardware many of the bookkeeping functions 
required to implement Master Control Program (MCP) re-entrancy. 



xxvi 1 



To provide dynamic storage allocation, the B 65OO system employs 
and expands upon the Burroughs descriptor method of segmentation, 
first used on the B 5500, in lieu of some form of fixed- sized 
"paging" technique. 

Designed to bring the user simplified programing, operational ease, 
and complete freedom of system expansion, the B 65OO offers a choice 
of three problem- oriented languages: COBOL for business applica- 
tions and ALGOL and FORTRAN for solution of mathematical problems. 
Operator intervention is minimized by the MCP, which provides for 
complete system management. 

The complete flexibility of programing and control of the proces- 
sing pattern provides the B 65OO with smooth growth potential. 
Starting with a minimum configuration, the user may expand his 
system in small increments to accommodate a growing work-load. 
With each addition, the MCP automatically adjusts to attain in- 
creased system production and efficiency, expanding system multi- 
programing capabilities. 

This reference manual describes the hardware characteristics of the 
B 6500 system. Because of the design concept of the B 65OO, there 
exists a strong interdependence between the hardware and the Master 
Control Program (MCP) . This material pertains only to the hardware 
considerations, whereas the MCP is discussed in a separate manual. 



xxv 111 



SECTION 1 
SYSTEMS DESCRIPTION 

GENERAL . 

This manual explains how the B 65OO Information Processing System 
achieves flexibility and efficiency through a comprehensive system 
approach to problem solving without considering the areas of com- 
puter logic or circuit design. The program- independent modular 
system design efficiently uses available units to process programs 
and also permits system configuration changes without the need to 
reprogram or recompile. This approach also offers the user the ad- 
vantages of simplified programing , ease of operation and a com- 
plete freedom of system expansion. The B 65OO is a compiler orien- 
ted system designed to accept the common languages; ALGOL, COBOL, 
and FORTRAN. The systems automatically handle memory assignments, 
program segmentation and subroutine linkages, eliminating many of 
the arduous programing tasks that are likely to produce errors. 
The programs are debugged and corrected at the source language 
level . 

DESCRIPTION OF UNITS . 

The B 65OO system configuration varies with application and work- 
load requirements. The basic system includes one processor, one 
maintenance test routine processor, one system control and one desk 
console. The maximum system configuration includes 2 processors, 
32 memory modules, 2 input/output multiplexors, 20 peripheral con- 
trols, 8 data communications processors, and 256 peripheral units. 
The central units are defined in table 1-1. The peripheral units 
available with this system along with their characteristics, are 
listed in Section 9 • The Data Communication Sub-System is de- 
fined in Section 10. 



1-1 



Table 1-1 
B 6500 Central Units Chart 



Style 






Number 


Description 


Notes 


B 6503 


Basic System 


2.5 megahertz clock 


B 6504 


Basic System 


5.0 megahertz clock 


B 6506 


Basic System 


5.0 megahertz clock 


B 6503-1 


Second Processor 


2.5 megahertz clock 


B 6504-1 


Second Processor 


5.0 megahertz clock 


B 6506-1 


Second Processor 


5.0 megahertz clock 


B 6713 


Multiplexor, 4 data switch- 


1 allowed per B 65O3 




ing channels 


system 


B 6713-1 


Additional data switching 
channel 




B 6714 


Multiplexor, 4 data switch- 
ing channels 




B 6714-1 


Additional data switching 
channel 




B 6716 


Multiplexor, 4 data switch- 
ing channel 




B 6716-1 


Additional data switching 
channel 




B 6000 


Optional Memory Control 
Cabinet 





1-2 



Table 1-1 (cont) 
B 6500 Central Units Chart 



Style 










Numb e r 




Description 


Notes 


B 6001-2 


98,304 


Bytes 


( 16,384 words) 


1.2 microsecond mem- 
ory for B 6503 and 
B 6504 systems. 


B 6002-2 


196,608 


Bytes 


( 32,768 words) 




B 6003-2 


294,912 


Bytes 


( 49,152 words) 




B 6004-2 


393,216 


Bytes 


( 65 , 536 words) 




B 6005-2 


491,520 


Bytes 


( 81,920 words) 




B 6006-2 


589,824 


Bytes 


( 98,304 words) 




B 6007-2 


688,128 


Bytes 


(114,688 words) 




B 6008-2 


786,432 


Bytes 


(131,072 words) 


B 6008-2 is the max- 
imum memory size per- 
mitted for the B 65O3 
system. 


B 6010-2 


983,040 


Bytes 


(163, 840 words) 




B 6012-2 


1,179,648 


Bytes 


(196, 608 words) 




B 6016-2 


1,572,864 


Bytes 


(262,144 words) 




B 6020-2 


1,966,080 


Bytes 


(327,680 words) 




B 6024-2 


2,359,296 


Bytes 


(393, 216 words) 




B 6032-2 


3,145,728 


Bytes 


(524,288 words) 





1-3 



Table 1-1 (cont) 
B 6500 Central Units Chart 



Style 












Number 




Description 




Notes 


B 6OOI-3 


98,304 


Bytes 


[ 16,384 


words ) 


600 nanosecond mem- 
ory for the B 6506 
systems . 


B 6002-3 


196,608 


Bytes 


[ 32,768 


words ) 




B 6003-3 


294,912 


Bytes 


[ 49,152 


words) 




B 6004-3 


393,216 


Bytes 1 


: 65,536 


words) 




B 6005-3 


491,520 


Bytes ' 


[ 81,920 


words ) 




B 6006-3 


589,824 


Bytes 1 


; 98,304 


words ) 




B 6OO7-3 


688,128 


Bytes 1 


[114,688 


words ) 




B 6008-3 


786,432 


Bytes 1 


[131,072 


words ) 




B 6010-3 


983,040 


Bytes 1 


[163,840 


words ) 




B 6012-3 


1,179,648 


Bytes 1 


[196,608 


words ) 




B 6016-3 


1,572,864 


Bytes l 


[262,144 


words ) 




B 6020-3 


1,966,080 


Bytes 1 


[327,680 


words ) 




B 6024-3 


2,359,296 


Bytes 1 


[393,216 


words ) 




B 6032-3 


3,145,728 


Bytes 1 


[524,288 


words ) 





1-4 



SYSTEM OPTIONS AND REQUIREMENTS . 

The following list of requirements and options are available for 

the B 65OO systems: 

a. A minimum of one special D.C. module is required in a 
B 65OO system. It can be installed in the following 
cabinets : 

1) Multiplexor. 

2) Processor. 

3) Peripheral Control. 

4) Data Communications. 

b. A minimum of one j+12 volt inverter module is required 

in a B 65OO system. It can be installed in the following 
cabinets: 

l) Multiplexor. 

2 ) Processor . 

3) Peripheral Control. 

NOTE 

This module precludes 
the use of any other 
module in a cabinet. 

c . A Flip Plop display supply module is required on the 
system and must be installed in the Multiplexor cabinet. 

d. The Memory cabinets each must contain a special Memory 
supply for developing the regulated voltages required 
for the memory operation. 

e. Each cabinet must contain an inverter for supplying power 
to its regulators. A 600 amp inverter is required in the 
Processor, Multiplexor and Data Communications cabinets. 
All other cabinets require a 400 amp inverter. 



1-5 



AUXILIARY CABINET. 

Peripheral unit exchanges are located within auxiliary cabinets on 
the B 65OO system. This cabinet can accommodate varying combinations 
oT exchanges depending on their physical size. Two of the various 
combinations that are possible are shown in figure 1-1. 





Figure 1-1. Auxiliary Cabinets 
The following exchanges are available for use on the B 65OO system. 

a. Tape Exchange 
2X10 

2X8 
4X16 

b. Disk File Exchange 
1X2 

2X5 

4X10 

4X20 

SYSTEM POWER. 

Main power is supplied to the system by 1 to 15 free standing A.C. 
power cabinets. Each power cabinet can furnish enough power for 
eight B 65OO cabinets. The power cabinets receive 3 phase A.C. from 
the wall breakers and convert it to 220 volt pulsating direct cur- 
rent. Each B 65OO cabinet contains an Inverter which supplies the 
regulated supply voltage required for use in its own component 
sections . 



1-6 



The AC module contains an AC control, the AC/DC converter and a 
OV/UV indication panel. Refer to figure 1-2 for a typical B 65OO 
power supply configuration. 



A. C. MODULE 



A.C. 
CONTROL 



OV/UV 
INDICATOR 



A.C. 
CONVERTER 




400A 
INVERTER 



MEM 
SUPPLY 



MEM 
REGULATOR 



MEMORY 



SEQUENCE CONT. 



MAI NT ./DISPLAY 



600A 
INV. 



FF 
DISPLAY 
MODULE 



MPX 




600A 
INVERTER 



±12V. 
SUPPLY 



PROCESSOR 



400A 



SPECIAL 

D.C. 
MODULE 



PERP. CONTROL 



Figure 1-2. B 65OO Power Supply 



1-7 



PERIPHERAL CONTROL CABINET. 

The PC cabinet can accommodate up to 10 peripheral controls . A max- 
imum of 5 large controls can be used with. 5 small controls, however, 
more than 5 small controls are possible if used in place of the 
large controls. 

The following controls are available: 

a. Large 

1. Magnetic tape 

2. Disk file 

3« Console Display 

b. Small 

1. Card reader 

2. Card punch 

3. Line printer 

k. Paper tape reader 
5 • Paper tape punch 

The large control has a two byte buffer and the small control con- 
tains a one byte buffer, therefore either 8 or 16 bits may be 
transferred in parallel to the Multiplexor at a time. Local opera- 
tions are performed by attaching a "Control switch." plug-on and two 
"Indicators" plug-ons to various cards in the control. 



SMALL 
CONTROLS 




LARGE 
CONTROLS 

OR 
SMALL 
CONTROLS 



Figure 1-3* Peripheral Control Cabinet 



1-8 



SYSTEM ORGANIZATION . 

Computer systems are generally organized around a central system 
that controls memory accesses, establishes I/O priority etc. In 
the B 65OO system this central control function has been distributed 
throughout the system by providing each peripheral unit with an 
associated control (figure 1-4). These peripheral controls, in 
conjunction with the multiplexor, provide independent but controlled 
access to main memory for each peripheral unit. The peripheral 
activity is supervised by the MCP which assigns outgoing data to 
the proper units or calls for required input data from others. 
Because the MCP is constantly aware of the available environment, 
the user program is efficiently executed whether units have been 
deleted for preventive maintenance or added because of increased 
work loads . 

MASTER CONTROL PROGRAM . 

The Master Control Program (MCP) provides overall system coordination 
and control of processing on the B 65OO system, minimizing operator 
intervention. The MCP obtains maximum use of the system components 
by controlling the sequence of processing, initiating all input/ 
output operations and providing automatic handling procedures to 
meet virtually all processing conditions. Because many functions 
are performed under MCP control, changes in scheduling, system con- 
figuration and program size are readily accommodated. 

CLOCKS. 

The MCP for the B 65OO makes use of two hardware clocks: The real 
time clock and the interval timer. The real time clock has a 2.4 
microsecond resolution and counts up to 24 hours. It is used by 
the MCP logging routines to provide extremely accurate timing in- 
formation and also can be read by application programs. This clock 
is associated with the multiplexor and runs continuously, even when 
the processors are halted. The interval timer is a clock (one in 
each processor) , which provides a predetermined timed interrupt for 
"time-slicing", loop hang-up etc. This interval varies from 512 
microseconds to one second, in 512 microsecond intervals. 



1-9 



16,384 TO 524,288 WORDS 
(98,304 TO 3,145,728 BYTES) 



MEMORY 




MEMORY 


MODULE 
1 




MODULE 
2 



MEMORY 

MODULE 

32 



UP TO 

32 

MODULES 



DATA 

COMMUNICATIONS 

PROCESSOR 



DATA 

COMMUNICATIONS 

PROCESSOR 



DATA 

COMMUNICATIONS 

PROCESSOR 



DATA 

COMMUNICATIONS 

PROCESSOR 



UP TO 
16 



ADAPTER 
CLUSTER 
NO. 16 



1-16 
LINES 



DATA 

COMMUNICATIONS 

NETWORK 



ADAPTER 
CLUSTERS 



ADAPTER 

CLUSTER 

NO. 2 



1-16 
LINES 



DATA 

COMMUNICATIONS 

NETWORK 



ADAPTER 

CLUSTER 

NO. 1 



1-16 
LINES 



DATA 

COMMUNICATIONS 

NETWORK 



1-16 ADAPTER 

CLUSTERS PER 

DCP 



INPUT/ 

OUTPUT 

MULTIPLEXOR 



DATA 

SWITCHING 
CHANNELS 
4-10 . 



PROCESSOR 
1 



PROCESSOR 
2 



INPUT/ 

OUTPUT 

MULTIPLEXOR 



DATA 

SWITCHING 
CHANNELS 
4-10 



DATA 

COMMUNICATIONS 

PROCESSOR 



DATA 

COMMUNICATIONS 

PROCESSOR 



DATS 

COMMUNICATIONS 
PROCESSOR 



DATA 

COMMUNICATIONS 

PROCESSOR 



*L 



ADAPTER 

CLUSTER 

NO. 1 



1-16 
LINEj^ 



DATA 

COMMUNICATIONS 

NETWORK 



1-16 ADAPTER 

CLUSTERS PER 

DCP 



i 



ADAPTER 

CLUSTER 

NO. 16 



1-16 
LINES 



DATA 

COMMUNICATIONS 

NETWORK 



Figure 1-k. B 6500 Schematic Diagram (sheet 1 of 2) 



1-10 



CARD 
READER 



CARD 
PUNCH 



PRINTER 



PAPER 

TAPE 

READER 



PAPER 

TAPE 

PUNCH 



| | 1 - 16 TAPE UNITS | j 



MAGNETIC TAPE EXCHANGE 



CARD 

READER 

PC 



CARD 

PUNCH 

PC 



PRINTER 
PC 



PRINTER 
PC 



PAPER 
TAPE 
READER 
PC 



PAPER 
TAPE 
PUNCH 
PC 



TAPE 
PC 



TAPE 
PC 



TAPE 
PC 



TAPE 
PC 



UP TO 5 MORE 
PERIPHERAL CONTROLS 



TAPE 
PC 



TAPE 
PC 



DISK 
PC 



MAGNETIC 
TAPE EXCHANGE 



TAPE 
PC 



ho 

1-16 TAPE 
_Q UNITS 



DISK 
PC 



DISK 
PC 



DISK FILE 
EXCHANGE 



TAPE 
PC 



DISK 
PC 



— Ql -20 1-20 Q - 

ELECTRONICS ELECTRONICS 

— Q UNITS UNITSQ— 



DISK FILE 
EXCHANGE 



DISK 
PC 



DISK 
PC 



Q 















TAPE 
PC 



TAPE 
CLUSTER 



CONS 

DISP 

PC 



CARD 

READER 

PC 



OPT 
PTR 




CONS 

DISP 

TERM 




CARD 




CARD 


KYBD 
FOR CD 






READER 




PUNCH 



CARD 

PUNCH 

PC 



PRINTER 
PC 



PRINTER 
PC 



PAPER 
TAPE 
READER 
PC 



PAPER 
TAPE 
PUNCH 
PC 



PAPER 

TAPE 

READER 



DISK 

PC 



PAPER 

TAPE 

PUNCH 



DISK 
PC 



DISK 
PC 



UP TO 4 MORE 
PERIPHERAL CONTROLS 



DISK FILE EXCHANGE 



1 



- 20 ELECTRONICS 
UNITS 



& 



Figure 1-4. B 6500 Schematic Diagram (sheet 2 of 2) 

1-11 



PROCESSOR . 

The B 65OO system accommodates either one or two processors, both 

capable of accessing any portion of total memory. 

All B 65OO processors are parallel machines; the B 6503 has a clock 
frequency of 2.5 megahertz, the B 6504/6506 a clock frequency of 
5 megahertz . Processors with different clock rates cannot be in- 
termixed on the same system. The processor is basically word ori- 
ented, but has extensive multiword string manipulation capabi- 
lities for 4-bit, 6-bit, and 8-bit characters. 

PROCESSOR STATES. 

The processor operates in either of two states: control state for 

the MCP or normal state for user programs and certain MCP functions, 

In a dual-processor system either processor may handle external 

interrupts. Both processors may be in control state at the same 

time. 

CONTROL STATE. Entry into a control state occurs when the proces- 
sor enters or returns to a procedure marked as a control state 
procedure, or executes a Disable External Interrupts operator. In 
control state the handling of external interrupts is inhibited 
while the processor executes privileged instructions not available 
in normal state. Exit from control to normal state occurs when- 
ever the MCP initiates a normal state procedure, exits back to a 
normal state procedure or executes an Enable External Interrupt 
operator. After an interrupt, return to the user's program may or 
may not be to the program that was operating when the interrupt 
occured . 

NORMAL STATE. Normal state excludes use of privileged instructions 
required by the MCP and allows external interrupts. Exit from nor- 
mal state occurs as a result of a Disable External Interrupt op- 
erator or by a call to a control state procedure; e.g., to initiate 
I/O. Many MCP functions are executed in normal state. 



1-12 



FEATURES . 

Some of the processor features areJ. 

a. Program code cannot be modified while in residence. 

b. Hardware stack features provide efficient handling of 
temporary storage and subroutine requirements. 

c. Control bits in each word provide efficient MCP or hard- 
ware action, depending upon the state of the control bits. 

d. Memory protection, which prevents one program from affect- 
ing another, is provided by a combination of hardware and 
software features. Hardware features include detection 

of program attempts to index beyond an assigned data area. 
Another feature includes the use of a memory protect bit 
in each word to prevent a user program from altering pro- 
gram segments, data descriptors, segment descriptors, mem- 
ory links, MCP tables, etc. The memory protect bits are 
set by the software. Attempts to alter information with 
this protect bit set will inhibit the write operation and 
generate an interrupt. 

e. The B 65OO processor is designed to implement higher-level 
languages and to function under MCP control. 

f . Major registers and control flip-flops in each of the pro- 
cessors contribute to system multiprocessing capabilities. 

INTERRUPT SYSTEM . 

The method of detecting and servicing system interrupts contributes 
to the ability of the B 65OO to process a mix of independent pro- 
grams in an efficient manner. Under the constant, automatic man- 
agement of the MCP, multiprocessing is the normal mode of operation. 
With one processor in the system, multiprograming (interlevel pro- 
cessing) is employed. A dual processor B 65OO System combines both 
multiprograming and parallel processing. The ability to multi- 
program, parallel process, or both is defined as multiprocessing. 



1-13 



Extensive interrupt facilities initiate specific routines in the 
Master Control Program (MCP) , Since the MCP maintains a central 
communications control, the interrupt transfers control to the MCP 
initiating operations that can proceed simultaneously with compu- 
tation. Some MCP functions are: data transfer control, input/ 
output control, error detection, etc. 

There are two interrupt conditions: Internal (Processor Dependent) 
or External (Processor Independent). Each processor in the B 65OO 
system is provided with a private internal interrupt network to han- 
dle the processor dependent interrupt. Interrupts generated with- 
in the processor are fed into this network and retained until ser- 
viced by that processor. The processors also share the handling of 
external interrupts generated by input/output operations occuring 
on either Multiplexor. The command structure in conjunction with a 
stack provides for implementation of string notation and automatic 
linking of subroutines. 

INTERRUPT HANDLING. 

An interrupt causes the processor to initiate the following sub- 
routine : 

a. Mark the stack. 

b. Insert an Indirect Reference Word into the stack, which 
addresses a reserved location of the stack where a link 
to the MCP interrupt routine has been stored. 

c. Push all pertinent registers into the stack. 

d. Insert into the stack an integer value defining the in- 
terrupt . 

e. Insert a second parameter into the stack, giving other in- 
formation about the interrupt. 

f . Execute an Enter operator. 



1-14 



The MCP processes the interrupt when it recognizes the Enter Op- 
erator. The MCP reactivates the interrupted object program by re- 
turning through the normal subroutine mechanism. 

OPERATOR DEPENDENT PROCESSOR INTERRUPTS. 

The interrupts listed below are set only by the action of operators, 

a. Presence bit. 

b. Invalid index. 

c. Exponent underflow. 

d. Exponent overflow. 

e. Interger overflow. 

f. Divide by zero. 

g. Invalid operand, 
h. Bottom of stack, 
i. Sequence error, 
j. Segmented array, 
k. Memory protect. 

1. Programed operator. 

Within a processor, only one operator dependent interrupt is set at 
any one time. 

OPERATOR- INDEPENDENT PROCESSOR INTERRUPTS. 
The operator- independent interrupts include: 

a. Memory parity. 

b. Stack overflow. 

c. Invalid address. 

d. Interval timer. 

e. Instruction timeout. 

f . Scan buss parity. 

g. Stack underflow. 

h. Invalid program word, 
i. MPX parity, 
j. Loop. 



1-15 



EXTERNAL INTERRUPTS. 

External interrupts are fed into the processor interrupt system. 
If the interrupt network is disabled on one processor, the external 
interrupt signal is routed to the other, since both processors in 
a dual-processor system are able to respond and process external 
interrupts independently and simultaneously. The ability of either 
processor to handle interrupts is made possible because of a dis- 
tributed interrupt network and the ability of both processors to be 
in control state at the same time. The activities of two proces- 
sors in control state are coordinated (interlocked) by the software 
through the use of the Read With Lock mechanism. If both proces- 
sors are handling interrupts, additional interrupts are retained 
for future processing. 

A unique literal value is assigned to each external interrupt con- 
dition. This literal value is transmitted to the processor and 
placed into the stack as the processor acknowledges the external 
interrupt and enters the interrupt sequence. 

The external interrupts include: 

a. Processor to Processor. 

b. I/O Finish. 

c. Data Comm. Att'n Needed. 

d. General Control Adapter. 

e. External Interrupt (piggyback MPX) . 

f. Change of peripheral-unit status. 

MAIN MEMORY. 



Main memory is expandable from one to eight modules on a B 6503 
system, and from one to 32 modules 011 B 6$0k and B 6505 systems. 
Each memory module contains 16,384 words permitting a current max- 
imum memory size of 524,288 words. Future provisions will allow 
for over one million words of storage. 



1-16 



MEMORY WORDS. 

Each memory word contains k8 information bits, three control bits, 
and a parity bit. The three control bits are used to identify de- 
scriptors, provide memory protection, describe the type of data, 
and provide other control functions. The twenty-bit binary combi- 
nations can provide up to 1,048,576 memory addresses, though pre- 
sently only 524,288 are used. Odd parity is used to check validity 
of information storage and transfers in the B 65OO system. 

Each system has a memory test facility used for fault detection and 
isolation. When the unit test facility is used to check one of 
the modules, the others are available to the system. 

MEMORY CYCLE TIMES. 

The memory cycle time is 600 nanoseconds for the B 65O6 systems 

and 1.2 microseconds for the B 6503 and B 6$0k systems. 

SECOND LEVEL MEMORY . 

Burroughs unique head-per- track disk file subsystem provides the 
user with virtually unlimited expansion capability. The 20 to 60 
millisecond average access time of the various disk file models 
permits extremely large programs and data segments to be stored on 
the disk and brought into main memory by the MCP when required. 

INPUT /OUTPUT MULTIPLEXOR. 

The Input/Output Multiplexor and associated peripheral control 
modules are used to control the transfer of data between memory 
and all peripheral equipment, independent of the processor. The 
multiplexor receives instructions from the processor and, with its 
associated peripheral controls, executes these instructions. One 
or two multiplexors may be used with the B 65OO System. Each multi- 
plexor is capable of processing up to ten simultaneous I/O opera- 
tions with up to 20 peripheral units. 

MULTIPLEXOR CONFIGURATION. 

Each multiplexor provides four separate and independent units: 



1-17 



a. Data switching channels which provide the necessary 
linkage between the peripheral device (excluding data 
communications) and main memory. 

b. Data communications processors which permit interfacing 
of remote devices to the B 65OO. 

c. A real time adapter which permits interfacing of real 
time devices such as wind tunnels and rocket stands. 

d. The peripheral system configuration tables for software 
use . 

DATA SWITCHING CHANNELS. 

The number of data switching channels determines the number of 
simultaneous I/O operations that can be performed. The channels 
float, assigned by the multiplexor to peripherals upon initiation 
of an operation and released to the multiplexor for reassignment 
upon completion. 

PERIPHERAL CONTROLS. 

Two types of peripheral controls are available, large and small. 
The large controls are used with high-speed devices such as mag- 
netic tape, disk files, and display consoles; the small controls 
are used with slower peripherals such as printers, card readers, 
and card punches. The large controls contain a two byte buffer 
and the small a one byte buffer. Each multiplexor can accommodate 
up to ten large and ten small controls. A small control may occupy 
a large control position. 

SYSTEM EXPANSION. 

The maximum configuration with two multiplexors (20 controllers per 
multiplexor) can be expanded further through the use of disk file 
and magnetic tape exchanges. Figure 1-5 illustrates a possible mag- 
netic tape subsystem. Figure 1-6 illustrates a possible disk file 
subsystem . 



1-18 



PERIPHERAL CONTROL BUS. 

A peripheral control (P.C.) bus extends from the multiplexor to the 
various peripheral controls (figure 1-7). Information in one- or 
two-byte groups can be sent along the bus to ot from any peripheral 
control every 1.2 microseconds. 



LARGE PERIPHERAL CONTROLS 




' Only 10 tape P.C.'sper 1/0 Multipl 
The 11th shown here is for i I lustra! 



purposes only. 



LARGE PERIPHERAL CONTROLS 



Figure 1-5. Possible Magnetic Tape Subsystem 



1-19 



PERIPHERAL CONTROLS 
LARGE 



1/0 

MULTI- 
PLEXOR 




MODEL 
B6373 








MODEL 




MODEL 
B 6373 
DISK FILE 
P.C. 










MODEL 
B6373 
DISK FILE 
P.C. 


MODEL 
B6373 
DISK FILE 
P.C. 


MODEL 
B6373 
DISK FILE 
P.C. 


MODEL 




MODEL 
B 6373 












DISK FILE 
P.C. 


P.C. 


DISK FILE 
P.C. 


P.C. 


DISK FILE 
P.C. 


DISK FILE 
P.C. 






































2 X 10 EXCH. 




N x N EXCHANGE 






















































1 TO 10 
ELECTRONICS UNITS 




1 TO 20 ELECTRONICS UNIT 








1 TO 5 

DISK MODULES PER 

ELECTRONICS UNIT 


1 TO 5 

DISK MODULES 

PER 

ELECTRONICS UNIT 


















I 
O 
X 

CN4 

z 
z 




in 

t— 

z 

o </> 

CN (J 

OZ 

i— 

UJ 


o 


O 

o 

a at 


l— 

Z 
o 

UJ 




































1 TO 5 

DISK 

MODULES 
























1 ELECTRONICS UNIT 


























I/O 

MULTI- 
PLEXOR 




MODEL 
B6373 


















MODEL 
B 6373 










DISK 
P.C. 


FILE 


P 


.<_. 






P. 








P. 






P. 


C. 




P.C. 




P. 






P.C. 


F 


.C 






DISK FILE 
P.C. 





PERIPHERAL CONTROLS 
LARGE 



Figure 1-6. Possible Disk File Subsystem 



INPUT/OUTPUT 
MULTIPLEXOR 



DATA 

SWITCH 

CHNLS. 



CARD 
READER 



B 91 12 



MODEL 
B 61 10 



APPROP. 

TAPE 

P.C. 



LINE 
PRINT 



B 9343-1 



MODEL 
B6240 



P.C. 



APPROP. 

TAPE 

P.C. 



1 TO 10 I/O 
UNITS OR SUB- 
SYSTEMS REQ. 
SMALL 
PERIPH. CONTLS. 



— I r— 

1 TO 10 

PERIPH. CONTLS. 

1 TO 10 

I L_ 



MA 
CLUSTER 



CONSOLE 
DISPLAY 
TERMINAL 
B 9342- 1 



Total per side is 10 with a 
maximum of 5 large per side 



I TO 10 1/0 UNITS OR 
SUBSYSTEMS REQ. LARGE 
PERIPH. CONTLS. 



CARD 
PUNCH 



B9213 



MODEL 

B6340 



P.C. 



APPROP . 

TAPE 

P.C. 



MODEL 
B6210 



P.C. 



MODEL 
B6373 



P.C. 




Figure 1-7- Input/Output Subsyste 



m 



1-20 



PROCESSOR INITIATED i/O OPERATIONS. 

Either processor can initiate an i/O operation on either multi- 
plexor (in a two processor/two-multiplexor configuration) by ex- 
ecuting an Initiate i/O command. This command transfers a Unit 
Number Word and an Area Descriptor to the multiplexor via the scan 
bus. The multiplexor then fetches the I/O Control Word located 
at the Area Base Address (in the Area Descriptor) and initiates 
the peripheral operation. An i/O Finished Interrupt is set after 
the peripheral operation is completed. The Result Descriptor is 
returned when either processor executes a Read Result Descriptor 
c ommand . 

PERIPHERAL CONTROLS. 

Up to 20 peripheral controls can be used with each i/O multiplexor. 
The peripheral controls are housed in one or two B 6^00 peripheral 
control cabinets. Each cabinet can accommodate 10 controls, five 
of which can be large controls and five small controls. The fol- 
lowing peripheral controls are available: 

a. Magnetic Tape. 

b. Card Reader. 

c . Card Punch. 

d. Line Printer. 

e. Paper Tape Reader. 

f . Paper Tape Punch. 

g. Disk File. 

h. Console Monitor and Keyboard. 

DATA COMMUNICATIONS PROCESSOR. 

Because the B 65OO is designed for continuous multiprocessing, the 
systems readily accommodate applications and procedures requiring 
data communications. Realtime operations, remote computing, remote 
inquiry, and on-line programing become additions to the multipro- 
cessing job mix of the B 65OO. The data communications processor 
is the heart of the data communications network. 



1-21 



The Data Communications Processor (DCP) is a small special purpose 
computer which contains sufficient registers and logic to perform 
all basic functions associated with sending and receiving data. Up 
to four DCP's can be connected to an I/O Multiplexor, with each DCP 
capable of accommodating from one to 256 communications lines (fig- 
ure 1-8). In a two Multiplexor system, this provides a B 65OO with 
the ability to service 2048 data communications lines. 



1-16 

ADAPTER 

CLUSTERS 



DATA 

COMMUN- 
ICATIONS 
PROCESSOR 



1-16 

ADAPTER 

CLUSTERS 



1-16 

ADAPTER 

CLUSTERS 



DATA 

COMMUN- 
ICATIONS 
PROCESSOR 



DATA 

COMMUN- 
ICATIONS 
PROCESSOR 



DATA 

COMMUN- 
ICATIONS 
PROCESSOR 



ADAPTER 
CLUSTER 
NO. I 



1 TO 16 
LINES 



DATA 

COMMUNICATIONS 

NETWORK 



ADDITIONAL ADAPTER 
CLUSTERS 2 THROUGH 15 



ADAPTER 
CLUSTER 
NO. 16 



1 TO 16 
LINES 



I/O MULTIPLEXOR 



Figure 1-8. Organization of Data Communica- 
tions Processor Remote Lines 

DATA COMMUNICATIONS ADAPTERS. 

Each communications channel requires an adapter which provides the 
logic to interface with a Data Set or to connect directly to a 
communications line. The following adapters are available: 



1-2; 



a. B 6650-1 with the following characteristics: 

1) Direct or modem connect. 

2) Asynchronous. 

3) Up to 600 BPS. 

4) Two wire or 100 series modem. 

5) Serial by bit transmission. 

6) Half-Duplex mode. 

b. B 6650-2 with the following characteristics: 

1) Direct or modem connect. 

2) Asynchronous. 

3) Up to 1800 BPS. 

4) Two wire or 202 series type Data Set. 

5) Serial by bit transmission. 

6) Half -Duplex mode. 

c. B 665O-3 with the following characteristics: 

1) Modem connect. 

2) Synchronous. 

3) Up to 2400 BPS. 

4) 201 series type Data Set. 

5) Serial by bit transmission. 

6) Half-Duplex mode. 

d. B 6650-4 same as B 66^0-3 except: up to 4800 BPS 

e. B 6650-5 same as B 665O-3 except: up to 96OO BPS 

f. B 665O-6 Touch-Tone® Telephone Input. 

g. B 665O-7 Audio Response. 

h. B 665O-8 Automatic Dial Out. 



® Registered Service Mark of A.T.T Co. 

1-23 



REAL TIME ADAPTER. 

An optional real time adapter may be attached to an i/o multi- 
plexor. Real time devices require custom engineering for inter- 
face with the real time adapter and the software. 



1-24 



SECTION 2 
DATA REPRESENTATION 

GENERAL. 

Several data representations are used in the B 6500 Information 
Processing Systems for word and character oriented data. Each word 
contains 48 information bits, three tag bits and one parity bit 
(figure 2-1). The data field may be a 48 bit single-precision oper- 
and, or a sequence of characters in 8-bit, 6-bit or 4-bit format. 
The tag bits in positions 50 through 48 are control bits which 
identify descriptors, provide memory protection, etc. The tag bits 
are inaccessible to normal state (user) programs. The parity bit 
in position 51 assures correct information transfer between the 
processor and main memory or from the scratch pad to main memory. 



5 5 4 4 4 
10 9 8 7 



*=^\ 



- CONTROL FIELD 
PARITY BIT 



v 

DATA FIELD 



Figure 2-1. Basic Word Structure 

INTERNAL CHARACTER CODES. 

Extended Binary Coded Decimal Interchange Code (EBCDIC) is the pri- 
mary internal character code of the B 65OO. EBCDIC is an 8-bit 
alphanumeric code containing 4 zone and 4 numeric bits. The Ameri- 
can Standard Code for Information Interchange (ASCII ) is the pri- 
mary data communication code. In addition, the Burroughs Common 
Language Code (BCL) provides interface compatibility with peri- 
pheral units. The pack operator allows greater packing density of 
numeric information by storing 4-bit digits in both the numeric and 
zone bit positions BCL and EBCDIC codes (figure 2-9) • 



2-1 



NUMBER BASES. 

Because the arithmetic operators are implemented in octal (base 8) 
and data display in registers and certain printed forms is Hexa- 
decimal (base 16), an understanding of both octal and hexadecimal 
numbering systems is useful. A brief discussion of binary and de- 
cimal numbering systems is also included. 

The decimal system is based on the ten digits, 0, 1, 2, 3? ^ > 5> 6, 
7, 8, and 9> and upon the powers of ten. Similarly, the binary 
system is based upon the two digits, and 1, and the powers of two 
Two raised to the third power (2 ) is 8, the base of the octal 
system. Likewise, 2 raised to the fourth power (2 ) is 16, the 
base of the Hexadecimal system. The decimal range for each number 
system is shown in figure 2-2. 



DECIMAL 


1 


23456789 


10 11 12 13 14 15 


BINARY 


1 






OCTAL 


1 


2 3 4 5 6 7 




DECIMAL 


1 


23456789 




HEXADECIMAL 


1 


23456789 


A B C D E F 



Figure 2-2. Number Base Graphic Characters 



The digits through 9 and the alphabetic characters A through F 
are used to cover the 16 character requirement for the hexadecimal 
numbering system. The letter A is assigned a value of 10, B equals 
11 etc. , to F which equals 15» 

HEXADECIMAL AND OCTAL NOTATION. 

Since binary words are cumbersome to display, the more efficient 
methods of Hexadecimal and Octal notation are employed. The hexa- 
decimal representation of a binary word is obtained by dividing the 
bits into groups of four with each group assigned a successive power 
of 16. A binary to octal conversion is obtained by dividing the 
bits into groups of three and assigning successive powers of 8 to 
each group (figure 2-3) • 
2-2 



Nxl6 



Nxl6 



Nxl6 



Nxl6 



Nxl6 



Nxl6 



-1 



Nxl6 















































8 








































































& 




~ 


b 






















" 
















4 






4 






4 






4 






4 






4 






4 








* 




* 
























HEXADECIMAL 






2 






2 






2 






2 






2 






2 






2 




1 


1 


1 


1 


1 


l 


1 








li- 






M 




t 




u 






n 






■ l 






a 


BINARY 


324 
288 


262 
144 


131 
072 


es 

536 


32 

768 


16 
384 


8192 


4096 


2048 1024 


612 


256 


128 


64 


32 


16 


8 


4 


2 


1 


% 


% 


1/8 


1/16 


1/32 


1/641/1281/256 



OCTAL 



BINARY 



Nx8 



Nx8 



Nx8 



Nx8 



Nx8 



Nx8 



Nx8 



-1 



Nx8 







































































4 






















4 






4 






" 












































2 






2 






2 






2 






2 






2 






2 






2 




1 


1 


1 


1 


l 


l 


1 


1 






i 


. 




i 


i 






n 






M 






n 






i. 






a 






M 


131 
072 


66 
536 


32 
768 


16 
384 


8192 


4096 


2048 


1024 


512 


256 


128 


64 


32 


16 


8 


4 


2 


1 


54 


% 


1/8 1 1/16 


1/32 1/64 



Figure 2-3. Binary to Hexadecimal and Octal Conversion 



The relationship between octal, decimal and hexadecimal is shown in 
figure 2-4 using the decimal number 1013 1Q (equivalent to 1765 g and 

( t.7-Vi qt-o -f-T-io anVi ar* ri T~>+: Pi . 1 O. OT" In "i 



3F5 n ^ where the subscript 8, 10, or 16 indicates the base). 



1765 =1x8 
° 1x512 
512 



+7x8 +6x8 
+ 7x64 + 6x8 
+ 448+48 



+ 5x8 = 
+ 5x1 = 

+ 5 ioi; 



10 



1013 = 1 x 10 3 + x 10 2 + 1 x 10 + 3 x 1 = 
1 x 1000 + x 100 + 1 x 10 + 3 x 1 = 



1000 + 
.3 



10 



= 1013 



10 



3F5. =0x16" + 3xl6 2 + F x 16 +5x16 = 
Ox 4096 +3x256+Fxl6+5xl = 



768 



240 



= 1013 



10 



Figure 2-4. 



Relationship of Octal, Decimal and Hexadecimal Numbers 

2-3 



NUMBER CONVERSION. 
CODED TO DECIMAL CONVERSION. 

The conversion to base ten of the integral value of a number whose 
base is other than ten may be accomplished by the addition of com- 
puted place positions as shown in figure 2-4. Another method of 
conversion is by repeated multiplications and additions as shown in 
figure 2-5 • The multiplier is the decimal value of the desired 
number base when using this system. 

DECIMAL TO CODED. 

The conversion of a Decimal number to any other base is accomplished 
by repeatedly dividing the number by the desired number base and 
retaining the successive remainders (figure 2-6). 



1 


1 ' 








1 

8 
8 J 


1 

^ 7 = 15 




x 8 , 
120 + t 


> = 126 






x 8 , 



1008 + 5 = 1013 



10 



3 F 5 .. (HEXADECIMAL NUMBER - MULTIPLY BY 16) 

16 



I L 



48 + 15 = 63 

x 16 i 



1008 + 5 = 1013 



10 



Figure 2-5. Hexadecimal and Octal To Decimal 



2-4 



126 
8| 1013 ]0 - REMAINDER 5 

15 



8 1 126 - REMAINDER 6 

1 
8 1 15 - REMAINDER 7-i 


8 1 1 - REMAINDER 1 

i 

17 6 5 



I J 





63 




16| 


,0,3 10 
3 


- REMAINDER -5 


16| 


63 



- REM = 15 = F 1 

- REMAINDER - 3 

1 ■ 

3 F 5 


16| 


3 



16 



Figure 2-6. Decimal 1013 To Hexadecimal and Octal 

DECIMAL AND HEXADECIMAL TABLE CONVERSION. 
(Use figure 2-7 for following computations.) 

Hexadecimal to Decimal. Find the decimal value for each hexadecimal 
digit according to its position. Add these to obtain the decimal 
equivalent . 

Decimal to Hexadecimal. Find the next lower decimal number and its 
Hexadecimal equivalent. Subtract and use difference to find the 
next decimal value and hexadecimal equivalent until the complete 
number is developed. 



2-5 





6 




5 




4 




3 


2 




1 




HEX 


DEC 


HEX 


DEC 


HEX 


DEC 


HEX 


DEC 


HEX 


DEC 


HEX 


DEC 






































1 


1,048,576 


1 


65,536 


1 


4,096 


1 


256 


1 


16 


1 


1 


2 


2,097,152 


2 


131,072 


2 


8,192 


2 


512 


2 


32 


2 


2 


3 


3,145,728 


3 


196,608 


3 


12,288 


3 


768 


3 


48 


3 


3 


4 


4,194,304 


4 


262,144 


4 


16,384 


4 


1,024 


4 


64 


4 


4 


5 


5,242,880 


5 


327,680 


5 


20,480 


5 


1,280 


5 


80 


5 


5 


6 


6,291,456 


6 


393,216 


6 


24,576 


6 


1,536 


6 


96 


6 


6 


7 


7,340,032 


7 


458,752 


7 


28,672 


7 


1,792 


7 


112 


7 


7 


8 


8,388,608 


8 


524,288 


8 


32,768 


8 


2,048 


8 


128 


8 


8 


9 


9,437,184 


9 


589,824 


9 


36,864 


9 


2,304 


9 


144 


9 


9 


A 


10,485,760 


A 


655,360 


A 


40,960 


A 


2,560 


A 


160 


A 


10 


B 


11,534,336 


B 


720,896 


B 


45,056 


B 


2,816 


B 


176 


B 


11 


C 


12,582,912 


C 


786,432 


C 


49,152 


C 


3,072 


C 


192 


C 


12 


D 


13,631,488 


D 


851,968 


D 


53,248 


D 


3,328 


D 


208 


D 


13 


E 


14,680,064 


E 


917,504 


E 


57,344 


E 


3,584 


E 


224 


E 


14 


F 


15,728,640 


F 


983,040 


F 


61,440 


F 


3,840 


F 


240 


F 


15 



HEXADECIMAL TO DECIMIAL 



DECIMAL TO HEXADECIMAL 



768 ♦■ 

240 ♦ 

+ 5*- 



1013 



10 



3 F 5 



16 



1013 

- 768 
245 

- 240 

5 



10 



F 5.. 
A A 16 



Figure 2-7. HEX and DEC Table Conversion 



2-6 



ORDER OF MAGNITUDE. 

The order of number magnitude in relation to the 39 bit mantissa, 

decimal numbers and powers of base 16, 8, and 2 are shown in figure 

2-8. 



REGISTER 
BIT SET 


NUMERIC 
EQUIVALENT 


HEX. 


OCTAL 


BINARY 





1 


1.0 


16° 


8° 


2° 


1 


2 


0.5 








2 


4 


0.25 




i 




3 


8 


0.125 




8 1 


2 3 


4 


16 


0.062 5 


16 1 






5 


32 


0.031 25 








6 


64 


0.015 625 




8 2 


2 6 


7 


128 


0.007 812 5 








8 


256 


0.003 906 25 


16 2 






9 


512 


0.001 953 125 




8 3 


2 9 


10 


1 024 


0.000 976 562 5 








11 


2 048 


0.000 488 281 25 








12 


4 096 


0.000 244 140 625 


16° 


8 4 


2 12 


13 


8 192 








14 


16 384 








15 


32 768 




8 5 


2 15 


16 


65 536 


16 4 






17 


131 072 








18 


262 144 




8 6 


2 io 


19 


524 288 


«; 






20 


1 048 576 


16 5 






21 


2 097 152 




8 7 


2 21 


22 


4 194 304 








23 


8 388 608 




n 




24 


16 777 216 


16 6 


8° 


T X 


25 


33 554 432 








26 


67 108 864 








27 


134 217 728 




8 9 


2 2 ' 


28 


268 435 456 


16 7 






29 


536 870 912 




in 




30 


1 073 741 824 




8 10 


2 30 


31 


2 147 483 648 








32 


4 294 967 296 


16 8 


1 1 


IT 


33 


8 589 934 592 




8 11 


2 33 


34 


17 179 869 184 








35 


34 359 738 368 


o , , 


1? 


1A 


36 


68 719 476 736 


16 ? 


8 12 




37 


137 438 953 472 








38 


274 877 906 944 




n 


39 


39 


545 755 813 888 




8 ,J 


2 JV 



Figure 2-8. Order of Magnitude Table 



2-7 



DATA TYPES AND PHYSICAL LAYOUT. 
CHARACTER TYPE. 

Character representation may be 8-bit bytes, 6-bit characters, or 4- 
bit digits. The 8-bit EBCDIC (Extended Binary Coded Decimal Inter- 
change Code) is the primary B 65OO code. When 8 or 6-bit numeric 
characters are used, the sign of the number is in the zone bits of 
the least significant character. Foi^ 4-bit digits, the sign is the 
most significant digit of the number. The number (-4259) is repre- 
sented as 8, 6, & 4-bit characters in figure 2-9« 



8-BIT BYTE EBCDIC CODE) 



TAG 




6-BIT CHARACTER (BCL CODE) 



IAG 


"01234567 





B 


4 














B 


X 


B 


4 


B 


X 


X 


4 





A 


2 














A 


2 


A 


X 


A 


2 


A 


2 





8 


1 














8 


1 


8 


1 


8 


X 


X 


X 



TAG 



4 2 5 

4-BIT DIGITS (PACKED EBCDIC OR BCL) 






8 


1 


2 


3 


4 


5 


6 


7 


8 
8 


y 

8 


10 


11 

X 





4 


















4 


X 







2 














2 


2 




2 


2 





1 














X 




1 











4 2 5 9 



Figure 2-9. (-4259) in 8, 6, and 4-Bit Code 



2-i 



Table 2-2 
Negative Sign Bit Configuration 





Siz e 




Sign Location 




Negative 


Positive 




8-Bit 


Zone j 


least significant 


char. 


1101 


Any bit con- 
figuration 




6-Bit 


Zone » 


least significant 


char. 


10 


other than the 




4-Bit 


Most 


significant digit 




1101 


negative com- 
binations . 



OPERANDS . 

Operands may be used to represent either numeric or logical infor- 
mation in the B 65OO system. An operand may be single or double- 
precision. The tag bits of a memory word (bits 50> 49 > 48) when 
zero, denotes a single-precision operand, and when two (bit 49 set), 
a double-precision operand. The structure of a single-precision 
operand is illustrated in figure 2-10 in a hexadecimal register 
format. Note that since the exponent is an octal scale factor, the 
single-precision operand is also shown in octal for reference. 
Figure 2-11 illustrates the double-precision operand in hexadecimal 
register format. 

An integer is a single-precision - operand with an exponent of zero. 
The maximum value of an integer is +7777777777777o , 549755813887 

or 7FFFFFFFFF., ,, 
16 

As an example, the decimal number 12 (l4o> ^i^') might be repre- 
sented in any of the following forms: 

a. In OCTAL format: 

0000000000000014 (integer) 

1010000000000140 

1020000000001400 ^(Floating point, or REAL) 

1131400000000000 



2-9 



b. In HEXADECIMAL format: 
00000000000C (integer) 
208000000060 

210000000300 J> (Floating Point) 
2A1800000000 



TAG 



EXPONENT 



MANTISSA 





47 




39 


















3 


50 


46 




38 


















2 


49 


45 




















5 


1 


48 


44 




















4 






OCTAL 
POINT 



Figure 2-10-A. Single Precision Operand 

[50:3] Tag field = for Single Precision Operand. 

[47:l] Unused. 

[46:1] Sign of operand = 1 for negative. 

[45:1] Sign of exponent = 1 for negative. 

[44:6] Exponent. 

The exponent is a binary number which with its sign, is an octal 
scale factor for the mantissa. The exponent is used for automatic 
scaling of operands when performing arithmetic, comparison and 
integer operations. The range of the exponent is from +63 to -63 
for single-precision operands. 

MANTISSA FIELD. 

The mantissa is the significant part of the operand. The magnitude 
of the operand is obtained by multiplying the value contained in the 
mantissa by eight raised to the value of the exponent sign and ex- 
ponent as follows : 

V=J:Mx8 : j : E 
V = Value of number 
_+M= Mantissa with sign 
+E= Exponent with sign 



2-10 



The range of numbers that can be expressed in single-precision is 
(8 13 -l) x 8 +63 to 1 x 8" 51 and zero. 



TAG EXPONENT 



MANTISSA 



50 


47 


44 




33 
























2 


49 


46 






























1 


48 


45 




39 
























3 






OCTAL 
POINT 



Figure 2-10-B. Single Precision Operand 



TAG EXPONENT 



MANTISSA 





47 




39 


















3 


50 


46 




38 


















2 


49 


45 






















1 


48 


44 




















4 






TAG EXPONENT 



(EXTENSION) MANTISSA 





47 




39 


















3 


50 






38 


















2 


49 
























1 


48 






















4 






FIRST 
WORD 



OCTAL 
POINT 



SECOND 
WORD 



Figure 2-11. Double-Precision Operand 

[50:3] Tag Field = 2 for double-precision operands. 

The first word of the operand is identical to the single-precision 
operand except for bit position 49, which indicates that this is one 
of a pair of words . 

The fractional part of the mantissa is contained in the mantissa ex- 
tension field of the word. 



2-11 



The 15-bit exponent of a double-precision operand is formed by the 
concatenation of the exponent extension with the exponent. The ex- 
ponent extension is more significant than the exponent. 

LOGICAL OPERANDS. 

Logical operands have one of two values: true (on) or false (off). 
Logical values are the result of Boolean operations or relational 
operations. Relational operators generate a logical value as the 
result of an algebraic comparison of two arithmetic expressions. 
Bit number zero (0) represents the logical value. Relational op- 
erators set bit number zero, and conditional operators use bit zero 
for the decision. Logical (Boolean) operators consider each bit, 
from 47 to bit 0, as an individual logical value, operating on the 
whole word. A logical value is expressed in the following form 
(figure 2-12). 





47 






















3 


50 


46 






















2 


49 


45 






















4 


49 


44 


























Figure 2-12. Logical Operand 



[50:3] =0 TAG = S.P. OPERAND 
[ 0:1] =1 TRUE, FALSE 

OPERATORS . 

The operators used in the B 65OO systems are divided into three 
major categories; Primary, Variant and Edit. Details regarding 
the format and function of these operators are found in Sections 
6, 7, 8, and 9. 



2-12 



SECTION 3 
STACK AND POLISH NOTATION 



THE STACK. 



GENERAL . 

The stack is an area of memory assigned to a job to provide storage 
for basic program and data references for the job. It also pro- 
vides for temporary storage of data and job history. When a job 
is activated, four high-speed registers (A, X, B, and Y) are linked 
to the job's stack (figure 3~l)- This linkage is established by 
the stack-pointer register (s), which contains the memory address 
of the last word placed in the stack. The four top-of-stack reg- 
isters (A, X, B and Y) extend the stack to provide quick access for 
data manipulation. 



IN/OUTPUT^ 



PATH OF DATA 
TO STACK 



TOP OF STACK REGISTER 



STACK'AREA 
ASSIGNED 
TO PROGRAM 



STACK AREA 
CURRENTLY 
IN USE 



WORDntx 



TOS WORD 



WORDn 



STACK 

MEMORY 

AREA 



r- S 



TOS WORD 



STACK LIMIT REGISTER 



LOS 



- H BOS 



Figure 3-1. Top of Stack and Stack Bounds Registers 



3-1 



Data are brought into the stack through the top-of-stack registers in 
such a manner that the last operand placed into the stack is the 
first to be extracted. Total capacity of the top- of- stack register 
is two operands. Loading a third operand into the top- of- stack reg- 
isters causes the first operand to be pushed from the top-of-stack 
registers into the stack. The stack-pointer register (s) is in- 
cremented by one as each word is placed into the stack and is de- 
cremented by one as each word is withdrawn from the stack and placed 
in the Top-of-Stack registers. As a result, the S register con- 
tinually points to the last word placed into the job's stack. 

BASE AND LIMIT OF STACK. 

A job's stack is bound, for memory protection, by two registers, the 
Base-of-Stack register (BOSR) and the Limit-of-Stack register (LOSR) . 
The contents of BOSR defines the base of the stack, and the LOSR 
defines the upper limit of the stack. The job is interrupted if the 
S register is set to the value contained in either LOSR or BOSR. 

BI-DIRECTIONAL DATA FLOW IN THE STACK 

The contents of the top-of-stack registers are maintained automa- 
tically by the processor to meet the requirements of the current 
operator. If the current operator requires data transfer into the 
stack, the top-of-stack registers receive the incoming data, and 
the surplus contents of the top-of-stack registers, if any, are 
pushed into the stack. Words are brought out of the stack into the 
top-of-stack registers for operators which require the presence of 
data in the top-of-stack registers, but do not explicitly move data 
into the stack. 

DOUBLE- PRECISION STACK OPERATION. 

The top-of-stack registers are operand-oriented rather than word- 
oriented. Calling a double-precision operand into the top-of-stack 
registers loads two memory words into the top-of-stack registers. 
The first word is loaded into the A register, where its tag bits 
are checked. If the value indicates double-precision the second 



3-2 



word is loaded into X. The A and X registers are concatenated, or 
linked together, to form the double-precision operand. The B and Y 
registers concatenate when a double-precision operand is moved to 
the B register. The double-precision operand reverts to single 
words as it is pushed from the B and Y registers into the stack. 
The concatenation is repeated when the double-precision operand is 
returned from the stack into the top-of-stack registers. 

DATA ADDRESSING. 

The B 6500 Processor provides three methods for addressing data or 

program code: 

a. Data Descriptor (DD)/Segment Descriptor (SD). 

b. Indirect Reference Word (iRW) . 

c. Stuffed Indirect Reference Word (SIRW). 

The Data Descriptor (DD) and Segment Descriptor (SD) provide for 
addressing data or program segments located outside of the job's 
stack area. The Indirect Reference Word (iRW) and the Stuffed 
Indirect Reference Word (SIRW) address data located within the 
job's stack. The IRW and SIRW address components are both relative. 
The IRW addresses within the immediate environment of the job rel- 
ative to a display register (described later in Non-local Addres- 
sing). The SIRW addresses beyond the immediate environment of the 
current procedure, and addresses relative to the base of the job's 
stack. Addressing across stacks is accomplished with an SIRW. 

DATA DESCRIPTOR. 

In general, the descriptor describes and locates data or program 
code associated with a given job. The Data Descriptor (DD) is 
used to fetch data to the stack or store data from the stack into 
an array located outside the job's stack area. The formats of the 
Data and Segment Descriptors are illustrated in Section 6. The 
ADDRESS field of both descriptors is 20 bits in length and contains 
the absolute address of an array in either system main memory or 
in the backup disk file as indicated by the Presence bit (P) . The 
referenced data is in main memory when the presence bit is set. 



3-3 



PRESENCE BIT. A Presence Bit interrupt occurs when the job ref- 
erences data with a descriptor which has its P bit and copy bit 
equal to ZERO. The Master Control Program (MCP) recognizes the 
Presence Bit Interrupt and transfers data from the disk file to 
main memory. After the data transfer to main memory is completed, 
the MCP marks the descriptor present by setting the P-bit to ONE, 
and places the new main memory address into the ADDRESS field of 
the descriptor. The interrupted job is then reactivated. 

INDEX BIT. A Data Descriptor describes either an entire array of 
data words, or a particular element within an array of data words. 
If the descriptor describes the entire array, the Index bit (l-bit) 
in the descriptor is ZERO, indicating that the descriptor has not 
yet been indexed. The LENGTH field of the descriptor defines the 
length of the data array. 

INVALID INDEX. 



A particular element of an array may be described by indexing an 
array descriptor. Memory protection is ensured during indexing op- 
erations by performing a comparison between the LENGTH field of the 
descriptor and the index value. An Invalid Index Interrupt results 
if the index value exceeds the length of the memory area defined by 
the descriptor, or if the index is less than zero. 

VALID INDEX. 



If the index value is valid, the LENGTH field of the descriptor is 
replaced by the index value, and the I-bit in the descriptor is set 
to ONE to indicate that indexing has taken place. The ADDRESS and 
INDEX fields are added together to generate the absolute machine 
address whenever a present, indexed Data Descriptor is used to 
fetch or store data. 

The Double-Precision bit (d) is used to identify the referenced 
data as single or double-precision and has a direct affect on the 
indexing operation. The D-bit equal to ONE signifies double-pre- 
cision and causes the index value to be doubled before indexing. 



?>-h 



READ-ONLY BIT. The Read- Only bit (r) specifies that the memory area 
described by the Data Descriptor is read-only area. An interrupt 
results when an area is referenced through a descriptor with inten- 
tions of storing with the R bit set to ONE. 

COPY BIT. The Copy bit (c) identifies a descriptor as a copy of 
a master descriptor and is related to the presence bit action. The 
copy-bit links multiple copies of an absent descriptor to the one 
master descriptor. The copy-bit mechanism is invoked when a copy 
is made in the stack, of an absent-Data Descriptor. If the Absent- 
Data Descriptor is the original (master) descriptor, the processor 
sets the copy bit to ONE and inserts the address of the master de- 
scriptor into the ADDRESS field. Thus, multiple copies of absent- 
data descriptors are all linked back to the master descriptor. 

POLISH NOTATION. 



GENERAL. 

To understand the B 65OO stack, Polish notation must be understood. 
A problem that exists with most forms of mathematical notation is 
defining the boundaries of specific terms. This is eliminated with 
the use of parentheses, brackets, and braces. The expression 5Z + 
7/2Z and (5Z + 7)/2Z express different functions of Z, but one 
could easily be used when the other was intended. However, with a 
complex equation, it becomes necessary to duplicate the use of the 
few types of delimiters that exist. 

Polish notation is an arithmetical or logical notational system 
using only operands and operators arranged in sequence or string 
which eliminates the necessity for defining the boundries of any 
terms. Figure 3-2 presents a flow chart for conversion to Polish 
notation. 



3-5 




-p 
u 

o 
> 

o 

H 

ft 

s 

o 

•H 
-P 

-P 
O 

Jz; 

en 
•H 

H 

o 

ft 



CM 
I 

U 

to 
•H 
ft 



3-6 



RULES FOR GENERATION OF POLISH STRING 
The source of expression is: 



Name 



Variable 



Operator- Separator 



Arithmetic or Boolean operator 
and last entered delimiter list 
symbol was : 

a. An operator of lower 
priority. 

b. A left bracket "[ " or 
parenthesis "(". 

c. A separator. 

d. Nothing (delimiter list 
empty. 

Arithmetic or Boolean operator 
and last entered delimiter list 
symbol was : an operator of pri- 
ority equal to or greater than 
the symbol in the source. 

A right bracket "] " or paren- 
thesis ")"• 



Action 



Place variable in string being 
built and examine next symbol. 

Place in delimiter list and ex- 
amine next symbol. 

Place operator in the delimiter 
list and examine next source 
symbol . 



Remove the operator from the de- 
limiter list and place in the 
string being built. Then compare 
the next symbol in the delimi- 
ter list against the source ex- 
expression symbol. 

Pull from delimiter list until 
corresponding left bracket or 
parenthesis . 



3-7 



POLISH STRING. 

The essential difference between Polish, and conventional notation 
is that operators are written to the right of the operands instead 
of between them. For example, the conventional B + C is written 
B C + in Polish notation: A = 7(B+C) becomes BC + 7 x A = . 

Any expression written in Polish notation is called a Polish string 
In order to fully understand this concept, the rule for evaluating 
a Polish string should be known. 

RULES FOR EVALUATING A POLISH STRING. 
The rule is summarized in a few steps: 

a. Scan the string from left to right. 

b. Remember the operands and the order in which they occur. 

c. When an operator is encountered: 

1) Record the last two operands encountered. 

2) Execute the required operation. 

3) Disregard the two operands. 

k) Consider the result of (2) as a single operand, the 
first of the next pair to be operated upon. 

Following this rule, the Polish string B C + 7 x A := results in A 
assuming the value 7 (B + c) (table 3~l)« 



3-i 



Table 3-1 
Evaluation of Polish String BC + 7 x A : = 



Step 


Symbol 

Being 

Examined 


Symbol 
Type 


Operands Being 
Remembered and 
Their Order of 
Occurence (l or 2) 
Before Operation 


Operation 
Taking Place 


Results of 
Operation 


a. 


B 


Operand 








b. 


C 


Operand 


1 B 






c . 


+ 


Add 
Operator 


2 C 
1 B 


B + C 


(B + c) 


d. 


7 


Operand 


l(B + c) 






e . 


X 


Multiply 
Operator 


2 7 

i(b + c) 


7 x (B + C) 


7 x (b+c) 


f . 


A 


Name 


1 7(B + C) 






g- 


: = 


Replace 


2A 










Operator 


1 7(B + C) 


A :^7(B + C) 


a=7(b + c) 



SIMPLE STACK OPERATION. 

All program information must be in the system before it can be used. 
Input areas are set aside for information entering the system and 
output areas are set aside for information exiting the system, array 
and table areas are allocated to store certain types of data. Thus 
data is stored in several different areas: The input/output areas, 
data tables (arrays), and the stack. Since all work is done in the 
arithmetic registers, all information or data is transferred to the 
arithmetic registers and the stack. 



3-9 



At this point, an ALGOL assignment statement and the Polish nota- 
tion equivalent will be related to the stack concept of operation. 
The example is Z : =Y + 2x(w+V) , where := means "is replaced by." In 
terms of a computer program, this assignment statement indicates 
that the value resulting from the evaluation of the arithmetic ex- 
pression is to be stored in the location representing the variable 
Z. 

When Z:=Y + 2x(w+v) is translated to Polish notation, the result is 
Y2WV+x+Z:=. Each element of the example expression causes a cer- 
tain type of syllable to be included in the machine language pro- 
gram when the source problem is compiled. The following is a de- 
tailed description of each element of the example, the type of 
syllable compiled, and the resulting operation (see figure 3-3 and 
table 3-2) . 

In the example statement, Y is added to a quantity; therefore, Y 
is brought to the stack as an operand. This is accomplished with 
a Value Call (VALC) syllable that references Y. The value 2 is 
then brought to the stack, with an eight bit literal syllable (LT8) . 
Since ¥ and V are to be added, the respective variables are brought 
to the stack with Value Call syllables. The ADD operator adds the 
two top operands and places the sum in the top of stack. This ex- 
ample assumes single-precision operands for simplicity not requiring 
use of the "X" and "Y" registers which are used in double-precision 
operations . 

The multiply operator is the next symbol encountered in the Polish 
string and when executed, places the product "2x(V+w) M in the top 
of the stack. The next symbol, ADD, when executed leaves the final 
result "7+2x(W+V)" in the top of the stack. 

Since Z is to be the recipient of a value, the address of Z must be 
placed into the stack just prior to the store command. This is ac- 
complished with a name call syllable which places an Indirect Refer- 
ence Word (iRW) in the stack. The IRW contains the address of Z in 
the form of an "address couple" that references the memory location 
reserved in the stack for the variable Z. 

3-10 




o 

< 
> 

z 


a 
< 








CM 


>- 


ST 

+ 

ST 

+ 

>- 


> 


£ 


> 







n 


> 






< 


£ 


> 




z 


+ 




> 



a 




_i 


> 


< 


+ 


> 


•5 


z 


CN 



| 








f 
































"> 




















N 


+ 






















* 








CM 


>- 


N 


> 


£ 


> 


Of 


CM 

+ 

>• 

























CN 


>- 


N 


>- 


£ 


> 







CN 


> 


N 


>- 


£ 


> 



o 

z 


> 

+ 








CN 


>- 


N 


> 


£ 


> 



o 

•H 
-P 
erf 



ft 
O 



+ > 




I* 



CN 


>- 







CN 


> 


N 


>■ 


£ 


> 









>■ 


til 


>- 


£ 


> 











til 


>- 


5 


> 





* 






I 










Q 




















< >- 


>- 


< 












w 


>- 


$ 


> 


> 




> 

z 





















o 



I 

en 

u 

•H 



2 2 
z z 














til 


>- 


£ 


> 



a < 
o 

o 



u u 



u u u u 



3-11 



Table, 3-2 
Description of Stack Operation 





Polish 


. 




Execution 


Notation 


Syllable Type 


Function of Syllable Dur- 


Sequence 


Element 


Compiled 


ing Running of the Program 









Stack location of pro- 
gram variables illustrated. 


1 


Y 


Value call 


Place the value of Y in 






for Y. 


the top of the stack. 


2 


2 


Literal 2. 


Place a 2 in the top of 
the stack. 


3 


¥ 


Value call 


Place the value of ¥ in 






for ¥. 


the top of the stack. 


k 


V 


Value call 


Place the value of V in 






for V. 


the top of the stack. 


5 


+ 


Operator Add. 


Add the two top words in 
the stack and place the 
result in B register as 
the top of the stack. 


6 


X 


Operator Mul- 


Multipl}^ the two top of 






tiply. 


the stack operands. The 
product is left in the B 
register as the top of 
the stack. (The A reg- 
ister contains the multi- 
plier and the B register 
the multiplicand.) 



3-12 



Table 3-2 (cont) 
Description of Stack Operation 





Polish 




■ 


Execution 


Notation 


Syllable Type 


Function of Syllable Dur- 


Sequence 


Element 


Compiled 


ing Running of the Program 


7 


+ 


Operator Add. 


Add the two top words in 
the stack and leave the 
result in the B register 
as the top of the stack. 


8 


Z 


Name call on 


Build an Indirect Ref- 






Z. 


erence Word that contains 
the address of Z and 
place it in the top of 
the stack. 


9 


: = 


Operator Store 


Store an item into mem- 






Destructive . 


ory. The address to store 
into is indicated by an 
Indirect Reference Word 
or a Data Descriptor. 
The address can be above 
or below the item stored. 





The Store syllable completes the execution of the statement Z : =Y + 
2x(W+v) . The store operation examines the two top of stack operands 
looking for an IRW or Data Descriptor. In this example the IRW ad- 
dresses the location where the computed value of Z is to be stored. 
The stack is empty at the completion of this statement. 



3-13 



PROGRAM STRUCTURE IN MEMORY. 

When a problem is expressed in a source language, portions of the 
source language fall into one of two categories. One describes the 
constants and variables that will be used in the program, and the 
other the computations that will be executed. When the source pro- 
gram is compiled, variables are assigned locations within the 
stack whereas the constants are embeded within the code stream that 
forms the computational part. A program residing in memory occupies 
separately allocated areas. Separately allocated means that each 
part of the program may reside anywhere in memory, and the actual 
address is determined by the MCP. In particular, the various 
areas are not assigned to contiguous memory areas. Registers with- 
in the processor indicate the bases of the various areas during the 
execution of a program. 

MEMORY AREA ALLOCATION. The separately allocated areas of a program 
are : 

a. Program Segments -- Sequences of instructions (syllables) 
that are performed by the processor in executing the pro- 
gram. Note that there is a distinction between program 
segments and data areas. The program segments contain no 
data, and are not modified by the processor as it executes 
the program. 

b. Segment Dictionary -- This is a table containing one word 
for each program segment. This word tells whether the 
program segment is in main memory or on the disk, and gives 
the corresponding main memory or disk address of the pro- 
gram segment. 

c. Stack Area -- This is the pushdown stack storage, which 
contains all the variables associated with the program, 
including control words which indicate the dynamic status 
of the job as it is being executed. 



3-14 



d. MCP Stacks and Segment Dictionary -- This area contains 

variables pertinent to the MCP. It also contains the MCP 
segment dictionary entries. Figure 3-4 shows in basic 
form the separately allocated areas of a program. 



n TjiT m 


OBJECT 

PROGRAM 

STACK 

CONTAINING 

VARIABLES 

AND 
DYNAMIC 
STATUS 




OBJECT 
PROGRAM 
CODE 
SEGMENT 
(n + 1) 


U |4J ■ •> 
D fa] •■ 
















r\ fol 






D [2J * 




OBJECT 
PROGRAM 
CODE 
SEGMENT 
(n) 










OBJECT 
PROGRAM 
SEGMENT 
DICTIONARY 




























OBJECT 

PROGRAM 

CODE 

OUTER 

BLOCK 

CODE 

SEGMENT 




S. D. PROG. 










S. D. PROG. 










D[l] — 


SEG. DEC. O. B. 


















MCP STACK 

AND 
SEGMENT 
DICTIONARY 












* 














D[0] — 







Figure 3-4. Object Program in memory 



3-15 



STACK- HISTORY AND ADDRESSING- ENVIRONMENT LISTS. 

One very important aspect of the B 65OO is the retention of the 
dynamic history for the program being processed. Two lists of pro- 
gram history are maintained in the B 65OO stack, the stack-history 
list and the addressing- environment list. The stack-history list 
is dynamic, varying as the job proceeds along different program 
paths with changing sets of data. Both lists are generated and 
maintained by B 65OO hardware. 

MARK STACK CONTROL WORD LINKAGE. The stack history is a list of 
Mark Stack Control Words (MSCW) , linked together by their DF fields 
(figure 3-5)* A MSCW is inserted into the stack as a procedure is 
entered, and is removed as that procedure is exited. Therefore, 
the stack history list grows and contracts with the procedural 
depth of the program. Mark Stack Control Words identify the por- 
tion of the stack related to each procedure. When the procedure 
is entered, its parameters and local variables are entered in the 
stack following the MSCW. When executing the procedure, its para- 
meters and local variables are referenced by addressing relative 
to the MSCW. 

STACK DELETION. Each MSCW is linked to the prior MSCW through the 
contents of its DF field to identify the point in the stack where 
the prior procedure began. When a procedure is exited, its portion 
of the stack is discarded. This action is achieved by setting the 
stack-pointer register (s) to address the memory cell preceding the 
most recent MSCW (figure 3-6). This top-most MSCW, addressed by 
another register (f), is deleted from the stack-history list by 
changing F to address the prior MSCW, placing it at the head of 
the stack history. 

This is an efficient and convenient means of subroutine entry and 
exit . 



3-16 



PROCEDURE B 



TOS WORD 



U 



ADDRESS STACK 

-ENVIRONMENT HISTORY 
LIST LIST 



MSCW 



DISP 



PROCEDURE A 



MSCW 



DF 



mIB=^L _QO~ 



PROCEDURE D 



MSCW 



TW 



PROCEDURE C 



MSCW 



OUTER PROG BLOCK ~ 



" l disp r ~ 



(MSCW) 



DISP 



DF 



IDF 



W^£=J 



Figure 3-5 • Stack History and Addressing Environment List 



i ~s~i 



. <, ±* *w,«< + 



>*****! 



***** 



TOS WORD 



-DISCARDED 
PORTION 
OF STACK 



MSCW 



STACK 

HISTORY 

LIST 



*> MSCW 




:D5Q±±f£ 



~ PROCEDURE "A' 



M 



DF 






MSCW 



PROCEDURE "D" 



DF 



Figure 3-6. Stack Cut-Back Operation on Procedure Exit 



3-17 



RELATIVE- ADDRESSING. Analyzing the structure of an ALGOL program 
results in a better understanding of the relative-addressing pro- 
cedures used in the B 65OO stack. The addressing environment of an 
ALGOL procedure is established when the program is structured by 
the programmer, and is referred to as the lexicographical ordering 
of the procedural blocks (figure 3-8) • At compile time, the lex- 



D REGISTERS 



D31 



D6 



D5 



D4 



D3 



D2 



Dl 



DO 



ADDRESS 
ENVIRONMENT 
STACK LIST 

MEMORY 
AREA ^ 



TOS WORD 



MSCW 



PCW-B 



V3 



MSCW 



V5 



MSCW 



PCW-D 



V4 



MSCW 



PCW-C 



PCW-A 



V2 



VI 



MSCW 



DISP 



DISP 



DISP 



DISP 



DISP 



'» u 



PROCEDURE B 



PROCE 



PURE A 



< 



PROCEDURE D 



PROCEDURE C 



OUTER PROG BLOCK 



Figure 3-7 • D Registers Indicating Current Addressing Environment 
3-18 



BEGIN 



REAL VI; 
REAL V2; 
PROCEDURE A; 



i — BEGIN 



REAL V3; 
PROCEDURE B; 

I — BEGIN • 



V3 — 3; 
Vl-*-V3; 



L— END; 



B 
END; 



PROCEDURE C; 
i — BEGIN 



REAL V4; 
PROCEDURE D; 



l — BEGIN 



REAL V5; 

V4-*-4; 

V5-»— 5; 

A; 

V2 V4; 



1 END; 



D; 
END; 



C; 
END; 



LEXICOGRAPHICAL LEVEL 2 
-^r = 2, 8 = 2 

-<^r = 2, 8 = 3 
^£= 2, 8 =4 

LEXICOGRAPHICAL LEVE L 3 
^€£ = 3, 8 = 2 
.-^ = 3, 8 = 3 

LEXICOGRAPHICAL LEVEL 4 



^€= 2, 8 = 5 

LEXICOGRAPHICAL LEVEL 3 

_^£» 3, 8 = 2 
-££ = 3, 8 = 3 

LEXICOGRAPHICAL LEVEL 4 
^Z= 4, 8 = 2 



Figure 3-8. ALGOL Program With Lexicographical Structure Indicated 



PROCEDURE B-i PROCEDURE "D" 



PROCEDURE A \P ROCEDURE "P"> 



OUTER PROGRAM BLOCK 




LEXICOGRAPHICAL LEVEL 4 



LEXICOGRAPHICAL LEVEL 3 



LEXICOGRAPHICAL LEVEL 2 



Figure 3-9. Addressing Environment Tree of ALGOL Program 



3-19 



icographical ordering is used to form address couples. An address 
couple consists of two items: 

a. The addressing level (JJJO of the variable, 

b. An index value (s) used to locate the specific variable 
within its addressing level. 

The lexicographical ordering of the program remains static as the 
program is executed, thereby allowing variables to be referenced 
via address couples as the program is executed. 

Base of Addressing- Level Segment . 

The B 65OO processor contains an array of D Registers (DO through 
D31) which address the base of each addressing-level segment (fig- 
ure 3-7) • The local variables of all procedures are addressed rel- 
ative to the D registers. 

Absolute Address Conversion. 



The address couple is converted into an absolute memory address 
when the variable is referenced. The addressing level portion of 
the address couple selects the D Register which contains the ab- 
solute memory address of the MSCW for the environment (addressing- 
level) in which the variable is located. The index value of the 
address couple is added to the contents of the D Register to gen- 
erate the absolute memory address. 

Multiple Variables With Common Address Couples. 

The address couples assigned to the variables in a program are not 
unique. This is true because of the ALGOL scope-of-def inition 
rules, which imply that two variables may have identical address 
couples if there is no procedure within which both of the variables 
can be addressed. This addressing system works because, whereas 
two variables may have the same address couples , there is never any 
doubt as to which variable is being referenced within any particular 
procedure . 



3-20 



Address Environment Defined. 

There is a unique MSCW which each D Register must address during the 
execution of any particular procedure. The D Registers must be 
changed, upon procedure entry or exit, to address the correct MSCWs . 
The list of MSCWs which the D registers address is the addressing 
environment of the procedure. 

Mark Stack Control Word Linkage. 

The addressing environment of the program is maintained automatically 
by linking the MSCWs together in accordance with the lexicographical 
structure of the program. This linkage is the Stack Number (Stack 
No.) and Displacement (DISP) fields of the MSCW, and is inserted 
into the MSCW whenever the procedure is entered. The addressing 
environment list is formed by linking each Mark Stack Control Word 
to the MSCW immediately below the declaration for the procedure 
being entered. This forms a tree- structured list which indicates 
the addressing environment of each procedure (figure 3-7 and 3-9) • 
This list is used to update the D Registers whenever a procedure 
entry or exit occurs. 

STACK HISTORY SUMMARY. The entry and exit mechanism of the Proces- 
sor hardware automatically maintains both the stack history and 
address- environment lists to reflect the current status of the pro- 
gram. Interrupt response is a procedure entry. Therefore, the 
system is able to respond to, and return from, interrupts conven- 
iently. Upon recognition of an interrupt condition, the proces- 
sor creates a MSCW, inserts an indirect reference word into the 
stack to address the interrupt-handling procedure, inserts a lit- 
eral constant to identify the interrupt condition and a second para- 
meter, and initiates an MCP interrupt-handling procedure. The D 
Registers are updated upon entry into the interrupt-handling pro- 
cedure, to display all legitimate variables. Upon return, the D 
Registers are updated to display variables of the former procedure. 



3-21 



MULTIPLE STACKS AND RE-ENTRANT CODE. 

The B 6500 stack mechanism provides a facility to handle several 
active stacks. These stacks are organized in a tree structure. The 
trunk of this tree structure is a stack which contains MCP global 
quantities . 

LEVEL DEFINITION. A program is a set of executable instructions, 
and a job is single execution of a program for a particular set of 
data. As the MCP is requested to run a job, a level-1 branch of 
the basic stack is created. This level-1 branch contains the Des- 
criptors the executable code and Read-only Data segments for the 
program. Emerging from this level-1 branch is a level- 2 branch, 
containing the variables and data for this job. Starting from the 
job's stack and tracing downward through the tree- structure , one 
finds first the stack containing the variables and data for the 
job (at level 2), the program code to be executed (at level l), and 
the MCP ' s stack at the trunk (level 0) . 

RE-ENTRANCE. A subsequent request to run another execution of an 
already- running program requires that only a level- 2 branch be 
established. This level- 2 stack branch sprouts from the level-1 
stack of the already- running program. Thus two jobs which are 
different executions of the same program have a common node, at 
level-1, describing the executable code. It is in this way that 
program code is re-entrant and shared. It comes about simply from 
the proper tree- structured organization of the various stacks with- 
in the machine. All programs within the system are re-entrant, in- 
cluding all user programs as well as the compilers and the MCP 
itself. 

JOB- SPLITTING . The B 65OO stack mechanism also provides the faci- 
lity for a single job to split itself into two independent jobs. 
A most common use of this facility occurs when there is a point in 
a job where two relatively large independent processes must be per- 
formed. This splitting could be used to make full use of a multi- 
processor configuration, or to reduce elapsed time by multiprogram- 
ing the independent processes. 

3-22 



A split of this type establishes a new limb of the tree- structured 
stack, with the two independent jobs sharing that part of the stack 
which was created before the split was requested. The process is 
recursively defined, and can happen repeatedly at any level. 

STACK DESCRIPTOR. Stack branches are located by an array of descrip- 
tors, the stack vector array (figure 3-10) • There is a data des- 
criptor in this array for every stack branch. This data descriptor, 
the stack descriptor, describes the length of the memory area as- 
signed to a stack branch, and its location in either main memory or 
disk. 



JOB JOB 

STACK STACK 
NO. n NO. 3 



JOB JOB 

STACK STACK 
NO. 2 NO. 1 



STACK 
VECTOR 
ARRAY 




D 
REGISTERS 



Figure 3-10. Multiple Linked Stacks 

A stack number is assigned to each stack branch. The stack number 
is the index value of the stack descriptor in the stack vector array 



3-23 



STACK VECTOR DESCRIPTOR. The stack vector array's size and location 
in memory is described by the stack vector descriptor. This des- 
criptor is located in a reserved position of the stack's trunk 
(figure 3-10) • All references to stack branches are made through 
the stack vector descriptor, indexed by the stack number. 

PRESENCE BIT INTERRUPT. A Presence Bit Interrupt results when an 
addressed stack is not present in memory. This Presence Bit 
Interrupt facility permits stack overlays and recalls under dynamic 
conditions. Idle or inactive stacks may be moved from main memory 
to disk as the need arises, and when subsequently referenced gen- 
erates a Presence Bit Interrupt to cause the MCP to recall the non- 
present stack from disk. 



3-2^ 



SECTION 4 
MAJOR REGISTERS AND CONTROL PANELS 

PROCESSOR REGISTERS. 

GENERAL. 

The Processor Registers and Flip Plops are displayed in the Display 

Cabinet of the system as shown in figure 4-1. Panel A displays the 

stack registers. Panel B is shared with the Multiplexor. Panels 

C, D, and E contain indicators and switches for the entire system. 




Figure 4-1. Processor Display Panels 

PANEL A (Refer to figure 4-2) 

A REGISTER. The A register is a 51 bit information register that 
holds one complete word. This register is the TOP OF STACK when 
AROF on indicates that it contains a valid word. It is used in 
many ways, arithmetic, boolean, character string, addressing, in- 
dexing, camparing, etc. 

B REGISTER. The B register is a 51 "bit information register con- 
sidered as the second word in the Stack when the A Register is valid 
It, too, has multiple usage such as arithmetic, boolean, character 
string, addressing, etc. The B register is valid when BROF is on. 



4-1 



C REGISTER. The C register is a 51 bit information register for 
general purpose use. It may contain an address, an IRW, an infor- 
mation word, a character or the "flash back" from a memory cycle. 

X REGISTER. The X register is a 51 hit information register used 
basically as the second word of a double-precision operand. 

Y REGISTER. The Y register is the counterpart of the X register 
for double-precision operands. It is the second-word of the B 
register operand. 

P REGISTER. The P register is a 51 bit instruction register. 

PANEL B (Refer to figure 4-3). 

Panel B indicators are shared by the Processor and Multiplexor 

Flip Flops. 

The PROC/MPX switches located on Panel C (Refer to figure k-k) 
control the display mode of this panel. 

Panel B is divided into related family and control, groups. The 
Maintenance Diagnostic Logic (MDL) Processor is common to both 
display modes. 

ROW A. This contains the Flip Flops for addressing the IC memories 
in the Memory Controller. 

BRSO =) BRS7 - Base read select thru 7 

IRSO =) IRS7 - Index read, select thru 7 

BWSO =) BWS7 - Base write select thru 7 

IWSO =) IWS7 - Index write select thru 7 

DRSO =) DRS5 - Display read select thru 5 

DWSO =) DWS5 - Display write select thru 5 

ROW B. This row contains the Flip Flops for the MDL Processor. 
There are three registers A01 => A10 , B01 =) B08 , and C01 =) C08 
associated with this processor. Each has a dual purpose depending 
on the use of MDL on i/o testing or system testing. The other 
Flip Flops in Row B are for MDL control. 

4-2 



PROCESSOR 



■eF 



© 
o 

TAG 



OOjO 
OjOO 

45 42 39 



ojo QidieTo ojoio'o ojo|©l 
o!orb qjojorb o!o o[o ojoj 

oL^OLQj^Wo QLQ]OlQ_Q\ 



>■ ReutTtR. 



'© 

o 
© 



OOjO 

oroo 

oLofb 



TAG 45 42 



o[b ojoiolo ojblorb 6]or©| 
ojorb ojolojO ojojorb oioi 



C REGISTER 



© 

o 
o 

TAG 



o ojolofo p]ofolo ojblo[b~p]or<§ 
o[o gjo 



r; 



["oolololboio 



O OOJOIO 
QIOJO OIDjOJO OJOlpjO OLOJOLQ©] 

45 4T 39 36 33 30 2? ^Ta 21 IB 15 12 IT 6 TT TT 



• X REGISTER < 



© 

o 
© 



o ojo 

oroo 

oLofb 



o 
o 
o 



TAG 45 42 39 36 33 30 



b bJoTbJo 
oroolojo 

Ldordojo 



fTSIr^lr- 



i 



27 24 



OjOiOOOjOf© 

[b ojo Ojb'oioj 

16 15 12 9 6 T () 



Y REGISTER 



© 

o 
o 

TAG 



r: 



O OjO 

orbo 
oloTo 

45 ^Z 39 



17 



r; 



OOJO!© 1 

o[b olo 



1 



ofb bjofolo ojolo 
olorbqjoofoolo 



P REGISTER" 



o 



o qjolofo djofblo ojbjo 
o[b ojojoFo olo|o[o ojo 
old oLoJolodjoLoJo © 

42 39 36 33 30 27 24 21 18 15 12 




fo bjoRi 
jofb ojo 
LqIoEqq 



Figure k-2. Processor Display Panel 



4-3 











PROCESSOR 








© ©0OOOO o 


K tifM WHITS StLtLI 

OOiOOOO 

DWS3 M7 NS3 BWS7 BWS3 


OOOOOO 

DAS3 IRS7 1RS3 **S7 ■**» 




oooooooo 


00 000 

DWS2 >**• *"** ***** BWS2 


OOOOOO 

DRS2 IRS6 IRS2 BRS6 BRS2 




oooooooo 


O OO OOO 
DWSS DWSI IWSS IWSI *WS5 BWSI 


OOOOOO 

DRSS DRSI IRS5 IRS I BRS5 BRSI 




oooooooo 


OOOOOO 

DWS4 DWSO 1WS4 IWSO *WS4 BWSO 


OOOOOO 

DRS4 ORSO »f4 JRSO BRS4 BR50 






o ooo 


OOOO 


OO, 


O 


OOOOO 


OOOO 




o ooo 

AROF LPF DISF 


OOOO 

MA 02 MA05 MAOB 


Q O 

B02F B06F 


O 

AOIF 


OOOOO 

A04F A07F A(OF C03F C06F 


OOOO 




o ooo 


OOOO 


OO 


O 


OOOOO 


OOOO 




ESTF CERF ERRl LOIF 

6 000 


MA03 MA06 MA09 

OOOO 


B03F B07F 

OO 


A02F 

O 


A05F A08F COIF C04F C07F 

OOOOO 


OOO© 




TNFF FECH ERR2 L02F 


MAOI MA04 MAO 7 MAlO B04F BOBF 

CORE AOORESS 1 TC NO 

MDL DISPLAY 


A03F 


A06F A09F C02F C05F C08F 
STRING NO 






■ FAMILY A 

O OOOOOOOO O 


OOOO 


, ARITH CONTROL 

OOOOOO 






TR03 JRA3 QROO(N) 0R04 QRtO NCR4 EBRO MYRO 

OOOOOOOOOO 


OOOO 


QRI4 CCAA A2CA EASI QCAA 

OOOOOO 






TRXI TR02 BBSZ JRA2 OR07 QR03 QR09 NCR3 EARO MBR2 




QRI3 CTAA A2AA EASZ OTAA 






OOOOOOOOOO 


OOOO 


OOO O-O 






0000000 00 


OOOO 


OOOOOO 






STRA TROO JRA4 JRAO OR05 QROOGMNCR5 NCRI MYRI MBRO 






ORll A4AA ATAA AASZO) EATA 

OOOOOO 




OOOO 


OOOOOOOO 


OO 




OB3F TB3F J67F JB3F 


QClF TR03 JC07 JC03 0C7F LL03 QCJF 




OROy EBTB FSL<#) FSRC0AAIZ FCBCg 






OOOO 


OOOOOOOO 


OO 


O O OOO Q 






QB2F TB2F JB6F JB2F 


STRK TR02 JC06 JC02 0C6F LL02 0C4F 




CINA EATB FSLOS FSRCO)ECBC FCBCfl) 






OOOO 


OOO OO OOO 


O O 


00 OOOO 

CTROClftBTBe FSLO(2)FCBB(2)E:BB FCBS(2' 






QBIF TBIF JB5F JBIF 


STRJ TROI JC05 JCOI QC2F LLOI CRUN 








OOOO 


OOOOOOOO 


OO 


O O O O O O 






TB4F TBOF JB4F JBOF 

FAMILY B 


STRC TROO JC04 JCOO LL04 LLOO NCSF 
FAMILY C 




AASI ATBB FSLCa'I)FCBB(I) ECBB FCBSW 






FAMILY D 

OOOOOO 


FAMILY I 

OOOOOOOOOOOOOO 






Q.03F TD3F JD7F JD3F QDBF QC7F 


0PR4 QEOI JEC8 KEOI CN08 D208 DB06 DI08 FC2A KE02 1CRB D1G8 






OOOOOO 


OOOOOOOOOOOOOO 






0D2F TD2F JD6F JD2F QDAF OD6F 


0PR3 QE02 JE04 CNCO CN04 0204 DB04 0104 0104 0204 0B04 1CR4 0IG4 






OOOOOO 


OOOOOOOOOOOOOO 






QDIF TDIF JD5F JOIF QD9F QD5F 


0PR2 QE03 JE02 CHOP CN02 D202 0B02 0102 0102 0202 0B02 K R2 DIG2 






OOOOOO 

TD4F TDOF JD4F JDOF 0O8F QD4F 


OOOOOOOOOOOOOO 

OPRS OPRI JEI6 JEOI CNI6 CNOI D20I DBOI OlOl CHOI 0201 Ofini ICRI DIGI 






OOOOOOOOOOOOOOOO 


OOOO 




VARF OPR6 JF03 JGOB DI06 SI08 EDIT O.FOI QHOI XROF EROS EXTF 






OOOOOOOOOOOOOOOO 


OOOO 




STBH 0PR4 KF03 JF02 KG03 JG04 0104 SI04 NVLF QF02 0H02 RPZF ER04 FLTF 






OOOOOOOOOOOOOOOO 


OOOO 




STB6 0PR2 KF02 JFOI K602 JG02 DSZ2 SSZ2 D]02 SI02 JGIF QF03 QH03 DGSF ER02 TFFF 






OOOOOOOOOOOOOOOO 


OOO© 




STBF OPRI KFOI JFOO KGOI JGOI 


r SZ 1 SS2 1 
FAMILY U — 


DIOI SIOI JFIF QF04 QHC 1 LHFF EROI OFFF 














OOOOOO 


O O 


O O 


OOOOOOOOOO 






012 F J 103 EXIA INVC SCC2 LTBI 




ACT8 J02F 


TRIP MAOF CZAF PET2 SMI9 SMI5 SMII SM07 SM03 






OOOOOO 

PTPI JI02 ITAR EXIB ICFF LTBO 


O O 


O O 

QS2F JOIF 


OOOOOOOOOO 

TIMO SPFF SUBF MI46 ^MIS SMI4 SMIO SM06 SM02 






OOOOOO 


O O 


O O 


OOOOOOOOOO 






SOIF J10I SUFL QUI- SCCI LOAO 




QSIF BROF 


TIMI MWRC PETO LPBF SMI7 SMI3 SM09 SMO'.. SMOI 






OOOOOO 


O O 


O O 


OOOOOOOOOO 






JI04 JIOO SDIS IIHF HLTD SCIL 




J03F AROF 


TJM2 REOF PETI MPEF SM20 SMI6 SMI2 SM06 SM04 SMOO 




OOOOOO 


O O 


O-O 


OOOOOOOOOO 




EDIT JP3F SECF INFF QP2F QPIF 




T0A3 T0M3 DIS3 XTZ6 Z6T9 






O.OO OOO 


OOO-O 


OOOOOOOOOO 






TEEF' JP2F CTIR PSR2 SSR2 CSR2 




T0A2 T0M2 0IS2 CTZ6 Z6L9 






000000 

YARF JP1F CPII P5RI SSRI C5RI 


OO-O-O 


OOOOOOOOOO 

T0A5 TOAI TOMS TOMI 0IS5 MSI BTZ6 Z6T6 






OOOOOO 


oM 


OOOOOOOOOO 






PROF JPOF CPIO PSfcO SSRO CS«0 




TOM TOAO T0M4 TOMO DIS4 DISO YTZ6 ATZ6 Z6L8 







D 



H 



Figure 4-3. Processor/Multiplexor Display Panel 



4-4 



ROW C. This row contains Family A Flip Flops and one half of the 
Arithmetic Controller Flip Flops. 



Family A. 
TROO => TR03 
JRAO =) JRA.4 
QR01 

qroo(a) 

QR02 

QR03 => QR07 

QR08 => QR10 

QR11 => QRl4 

QR15 
QR00/QR01 

qroo(n)/cina 

NCRO => NCR5 

MBRO =) MBR2 

MYRO =) MYR2 

EARO 

EBRO 

STRA 

XX A 1 
TRX1 



Contains the OP Code 

Sequence Count used in the OP Code flow 

Pre- Carry INTO Adder 

Carry-in set control 

High-speed clock phase control 

Logic control 

Temporary storage 

Q Counter 

Interrupt flip flop 

Carry-in reset control 

Multiple control 

N Counter 

B Register Mantissa Field Extension 

Y Register Mantissa Field Extension 

Extension of A Register Exponent Field 

Extension of B Register Exponent Field 

Family A Strobe F.F. (turned on by the Program 
Controller thru the Z10 bus) 

Function Parallels STRA 

Function Parallels TR01 



Arithmetic Control. 

All other Flip Flops in this Controller are used for logic control 

They are : 



BBSZ 
AAS1 
ETBT 
EATB 
BTBB 
ATBB 
FSLC (l) 
FSLC (2) 



FCBB (2) 
FSRC (l) 
FSRC (2) 
AA1Z 
ECBC 
ECCB 
ECBB 
FCBC (l) 



h-5 



FSLC (5) FCB1 (2) 
FSLC (6) FCBS (l) 
FCBB (l) FCBS (2) 

ROW D. This row contains the Family B and C Flip Flops. 

Family B. 

TBOF => TB4F - Contains the OP Code 

JBOF =) JB6F - Sequence Count used in the OP Code flow 

QB1F =) QB4F - Logic Control 

Family C. 

TROO => TR03 - Contains the OP Code 



JCOO =) JC07 - Sequence Count used in the OP Code fl 



ow 



LLOO =) LL04 - Lexicographical level Flip Flops for the 

Program flow 

STRC - Strobe Family C ( Sub-routine ) 

STRJ - Strobe Family J (Value Call) 

STRK - Strobe Family K (Name Call) 

QC1F => QC8F - Logic Control 

NCSF - Normal Control State Flip Flop OFF signifies 

Normal State 

The Control State Flip Flop extends the Operator set to include 
some additional Operators and disables external interrupt detection 
by the Processor. 

CRUN Family C Run Flip Flop 

ROW E. This row contains the Family D and E Flip Flops. 

Family D. 



k-6 



TDOF Family D Strobe 

TD1F =) TD4F - Contains the OP Code 

JDOF =) JD7F - Sequence Count used in OP Code flow 

QDIF =) QD9F, QDAF, QDBF - Logic Control Flip Flops 

Family E. 

OPRS - Family E Strobe 

0PR1 =) 0PR4 - Contain the OP Code 

JE01 =) JE16 - Sequence Count used in OP Code flow 

DIG1 =) DIG8 - Length Field 

ICR1 =) ICR8 - Input Convert 

0B01 =) 0B04 - Octal Buffer Bit 

0101 => 0104 - Octal 1 bit 

0201 => 0204 - Octal 2 bit 

DB01 =) DB08 - Digit Buffer Bit 

D101 => D108 - Digit 1 Bit 

D201 =) D208 - Digit 2 Bit 

CN01 =) CN16 - Counter 

QE01 =) QE03 - Logical Control 

ROW F. This row contains the Family U (String OP) Flip Flops. 

Family U is the hardware logic for the STRING OP CONTROLLER. 

0PR1 =) 0PR8 - Contains the OP Code for this controller 

KF01 =) KF03 - Extension of Sequence count for family F 

JFOO =) JF03 - Sequence Count used in Family F OP Code flow 

KG01 =) KG03 - Extension of Sequence count for family G or H 

JG01 =) JG08 - Sequence Count used in Family G or H OP Code flow 

VARF - Variant Flip Flop to alter the OP Code 

DSZ1 - Destination Size Less Significant Bit 

DSZ2 - Destination Size More Significant Bit 

SSZ1 - Source Size Less Significant Bit 

SSZ2 - Source Size More Significant Bit 

DI01 =) DI08 - Destination Character Pointer 

SI01 =) SI08 - Source Character Pointer 

EDIT - Edit Mode for String OPS 



h-1 



NVLF 
JGIF 
JFIF 
QF01 
QF02 
QF03 
QF04 



Invalid OP Code 



JG Interrupt State 



JF Interrupt State 



Invalid OP Interrupt 



Presence Bit Interrupt 



Memory Protect Interrupt 



Segmented Array Interrupt 



QH01 => QR01 - Logical Control 



XROF 



RPZE 



DGSF 



LHFF 



ER01 =) ER08 



EXTF 
FLTF 
TFFF 
OFFF 



Register Occupied 

Logical Control 

Logical Control 

Logical Control 

E Register Flip Flops (used Tor Memory Cycle 
requests during String OP Code flow) 

External Sign 

Float 

True False 

Overflow 



ROW G. This row contains the Flip Flops for the Interrupt Con- 
troller, the Stack Controller and the Memory Controller. 

Interrupt Controller. 

JIOO =) JI04 - Sequence Count for Controller Flow 
S01F - Stack Overflow 

PTPI - Processor to Processor Interrupt 



4-8 



QI1F, QI2F 

EXIA 

EXIB 

I TAR 

SUFL 

SDIS 

SCC1, SCC2 

ICFF 

HLTD 

LOAD 

SCIL 

LTBO , LTB1 



Logical Control 

External Interrupt A (MPX-A) 

External Interrupt B (MPX-B) 

Interval Timer Armed 

Stack Underflow 

Syllable Dependent Interrupt 

Scan Counter Bit 1 and 2 

Interrupt Controller Run 

Halted 

Load 

Scan Interlock 

Load Timer Bit 



Stack Controlle r. 

J01F => J03F ■ 

ACT8 

QS1F, QS2F 

AROF 

BROF 



Sequence Count for Controller flow 

Address Couple to Z8 bus 

Logical Control 

The A Register Contains a Valid Word 

The B Register Contains a Valid Word 



Memory Controller. 

SMOO =) SM20 - Address Adder Output Flip Flops. These are for 

display only. (No Manual Set or reset Controls) 



TRIP 



Trip Control Invalid Address 



TIMO => TIM2 



MA OF 



Invalid Address Timer 



Memory Address Obtained 



SPEF 



Scan Bus Parity Error 



MWRC 



Memory Write Control 



REQF 
CZAF 
SUBF 



Memory Request 



Carry Zero Control 



Address Adder Subtract 



k-9 



PETO =) PET 2 

MI48 

LPBF 

MPEF 



Information Parity Test Control Register Bit 

Memory Protect Bit 

Line Parity Bit from Memory 

Memory Parity Error 



ROW H. This row contains the Flip Flops for the Program Controller 
and Transfer Controller. 

Program Controller. 

JPOF =) JP3F - Sequence Count for Controller Flow 



PROF 
VARF 

TEEF 
EDIT 
CPIO, CPU 

CTIR 

SECF 
INFF 

PSRO => PSR2 

QPIF, QP2F 
SSRO =) SSR2 

CSRO => CSR2 



The P register contains a Valid Word 

Variant Mode FF (used to escape to 16 Bit 
Instruction) 

Table Enter Edit 

Edit Mode 

A 2 bit counter used to back up the PIR (Program 
Index Register) 

A 1 bit counter used to back up the TIR (Table 
Index Register) 

Seel (Syllable Execute Complete Level) Saved 

Inhibit Fetch FF (used to inhibit bringing a new 
program word to the P register) 

Program Syllable Register 0=>5 Pointer (Points to 
next syllable to be executed from the P register) 

Logic Control 

Syllable Saved Register (used to save the current 
position of PSR when in Table Mode) 

Command Syllable Register 0=) 5 (used to save the 
current position of PSR) 



4-10 



Transfer Controller. 



TOAO =) T0A5 



TOMO => T0M5 



DISO => DIS5 

YTZ6 
XTZ6 
CTZ6 
BTZ6 
ATZ6 

Z6L8 
Z6T9 
Z6L9 
Z6T9 



Top of Aperature Flip Flops (used to select top bit 
of 48 bit field to be transferred thru the steering 
and mask network) 

Top of Mask Flip Flops (used to select top bit of 
48 bit field to be inhibited thru the steering and 
mask network) 

Displacement Flip Flops (used in steering network 
to logically displace bits of a 48 bit field) 

Gating Flip Flops to the Z6 bus. (Allows the 
contents of the various registers to be gated to 
this bus) 



Z6 Bus Lower to Z8 Bus (Allows bits ±3 ilk to be 
transferred) 

Z6 Bus Top to Z8 Bus (Allows bits 39:20 to be 
transferred) 

Z6 Bus Lower to Z9 Bus (Allows bits 35:16 to be 
transferred) 

Z6 Bus Top to Z9 Bus (Allows bits 39:20 to be 
transferred) 



GENERAL MAINTENANCE CONTROLS. 

The maintenance control panel shown in figure 4-4 is panel C. It 
contains the indicators and necessary controls for maintenance of 
the B 6500 system. Units which cannot be controlled from this 
panel have their own local maintenance controls. 



4-11 



POWER CONTROLS. 

Power supplied to the B 65OO system can be controlled by two se- 
quence control circuits. (Sequence Control Circuit A and B). There 
are two sets of power control switches located on the upper-right 
corner of panel C. These are the power- on switch and the power- off 
switch. One set controls sequence control A, and the other controls 
sequence control B. Besides the power on and off switches there is 
a set of three toggle switches labeled connec t-disconnec t , "A", "B", 
or "C". These switches establish the mode in which the "Power on 
and off" switches are used. When switches A, B, and C are in the 
disconnect position they indicate that power section "A", "B", and 
"C" are controlled independently by their respective switches. When 
switch "C" is in the connect position, we can connect power section 
"A", and "B" to a third section "C" and have a common control. 



Lamp indicators "1, 2, k, and 8" indicate the failure of one of 15 
AC modules. For example, if AC module #7 has failed, indicators 
labeled "1", "2" and "4" will turn on. 

GENERAL CLEAR AND HALT- LOAD FUNCTION. 

On the upper- right corner of the control panel there are two push- 
button switches labeled "General Clear A, and General Clear B". 
The domain of each of these switches depends on the positions of 
switches A, B, And C are in the disconnect mode, section A is 
cleared with the "GEN CLEAR A" switch, and section B is cleared 
with the "GEN CLEAR B" switch. If a third section "C" exists, it 
will have its own general clear. If switches A, B, and C are in 
the connect positions, sections A, B, and C are cleared whenever 
either one of general clear switch A or B is depressed. 

There is no direct clear switch located at the operator's console; 
however, system's general clear from this unit is provided through 
the "load" switch. Whenever the load switch is depressed, the 
system is automatically cleared before the load command is executed 



4-12 



The "HALT", "LOAD", and "CARD LOAD SELECT" switches are duplicated 
at the maintenance panel (panel C) for convenience of operation. 
These switches are located in the lower-left corner of panel C. 

System's clear through Load Switch: When the "load" switch at 
either the console or the maintenance panel is depressed, a clear 
signal is generated. Both sections A and B are cleared. When the 
load switch is released, the load logic generates the load command 
which is transmitted to the data processors. 




POWER CONTROLS 







8 4 2 1 OFF ON GEN CLEAR 

* 6 * CONNECT CK>70 

A B C- DISCONNECT OFF ON GEN CLEAR 

PROC REG CLEAR 




A B C X 

MPX REG CLEAR 



Y P 

MDL REG CLEAR- 





C T TOD AC B 
MDL CONTROLS 



MC 




[ 



LOAD STOP RUN DIAGNOSE HALT CYCLE LOCK CLEAR 
SYST -|i CLOCK CONTROLS ■ ■- DISP 




ON 



HALT OFF 





LD SLCT PULSE 
TRAIN 



,MDTR 



iroNi 

II ifti l 



NORMAL SYST PROC-1 MPX-1 OFF 

PROC-1 

01 10) I0) OFF 

MDL DISPLAY PROC-2 MPX-2 | PROC-2 



MPX-1 





™ - - ~ ^ Iv^l 

LOAD SINGLE B2 Bl BO FFRESET MPX " 2 

PULSE 





OFF 



Figure k-k. Panel C General Controls 



4-13 



PROCESSOR REGISTER CLEAR. 

A set of six pushbutton switches is provided, for individual clear 
of registers A, B, C, X, Y and P of the Data Processor selected 
by the display select switch. 

MULTIPLEXOR REGISTER CLEAR. 

The Multiplexor registers may be individually cleared with the 

switches listed below: 

a. Switch D clears the Data Register. 

b. Switch C clears the Command Register. 

c. Switch T clears the Tag Register. 

d. Switch TOD clears the Time of Day Register. 

MDL REGISTER CLEAR. 

The MDL registers may be individually cleared with the switches 

list e d b e 1 o w : 

a. Switch MC clears the Core Address. 

b. Switch B clears the TC No. 

c. Switch AC clears the String No. 

MDL CONTROL SWITCHES. 

This group of switches is used for loading and controlling the 

Maintenance Diagnostic Logic. 

DISPLAY SELECT SWITCHES. 

This group of switches is composed of three toggle switches located 
in the lower- right corner of the panel. The function of these 
switches is as follows: 

a. On- Off Switch: This switch enables or disables the 
display logic . 



k-lk 



b. Processor Select Switch: This is a three-position toggle 
switch which selects which of two processors is scanned by 
the MDL. 

c. Multiplexor Select Switch: This is a three-position toggle 
switch which selects which of two multiplexors is scanned 
by the MDL. 

CLOCK CONTROLS. 

The clock control switches provide the means of inhibiting the 

system clock to the various components of the system. 

Clock toggle switches when activated in the "up" position inhibit 
the following. 

Entire system 

Processor #1 

Multiplexor #1 

Maintenance Diagnostic Processor 

Display Logic 

Processor #2 

Multiplexor #2 

SINGLE PULSE SWITCH. 

This switch is used to produce a single clock when the clock has 

been inhibited. 

PULSE TRAIN SWITCH. 

This switch is used to produce a train of pulses. Each depression 
produces all the clock pulses that normally appear within a 500 nano 
second period. 

INDICATORS BO, Bl , B2 . 

These indicators indicate the logical time division of the Pulse 

Train. 

MDTR/NORMAL SWITCH. 

This switch is used to change the system from a normal mode of op- 
eration to that of Maintenance Diagnostic Logic. 

k-15 



a. 


SYST 


b. 


PROC-1 


c . 


MPX-1 


d. 


MDL 


e . 


Display 


f . 


PROC-2 


£. 


MPX-2 



FF RESET SWITCH. 

This switch when depressed indicates that a flip-flop in the unit 

selected is to be reset. 

HALT, LOAD, and LOAD SELECT SWITCHES. 

The function of these switches is the same as their corresponding 
switches at the console. The Halt Switch is used to halt the system 
in an orderly manner. The Load Switch is used to perform a Load 
Operation as per the positions of the Load Select Switch. The Load 
Select Switch is used to select a Disk or Card Load operation. 

The indicator is lit when Card Load is selected. 

NOTE 

For a detailed description 
of the Load operation refer 
to the description of the 
Operators panel (Section 4) . 

PROCESSOR MAINTENANCE CONTROLS (Panel E) . 

Each processor is provided with an independent maintenance control 
panel. These controls are additions over and above the console 
controls (Halt, load, power on/off ---, etc.) and the general system 
controls (Panel C). 

The I. C. Memory registers of the processor are not displayed by 
the system's display unit; however, certain switch controls located 
on the processor control panel allow control and display of these 
registers . 

The control switches provided on the processor control panel and 
their related functions are described in this section. Reference is 
made to figure 4-6 which shows a front view of Panel E. 

START SWITCH. 

The start switch is a pushbutton type switch which functions to 

start, a halted processor, to execute the next operator syllable 



4-16 



s 



pointed to by "PSR", "PIR", and "PBR". This switch is active only 
when the processor's clock is enabled and when depressed activates 
the "SECL" switch to cause the execution of the next operator syl- 
lable to be initiated in the normal manner. 

CONDITIONAL HALT SWITCH. 

This switch is a 2 position toggle switch which functions to enable 
the conditional halt operation to stop the data processor. The 
conditional halt operator functions as a "No-Op" when executed with 
the "CONDITIONAL HALT" switch in the down position and functions to 
stop the data processor when in the up position. 

STOP SWITCHES. 

The following set of stop switches enable the data processor to 
stop upon the occurrence of specified conditions. The exact action 
of these switches is modified by the position of the "STOP MODE" 
switches . 

SECL SWITCH. 

The SECL switch when in the "up" position causes the processor to 
stop after the execution of each operator syllable. It activates 
the "INPL" (inhibit fetch level). 

INT- I SWITCH. 

The stop on internal interrupt switch (iNT-l) causes the data 
processor to stop upon the occurrence of an internal interrupt 
condition, when in the "up" position. The data processor stops 
displaying both the PI and P2 interrupt parameters in the A and B 
registers just prior to entering the interrupt procedure. 

EXT- I SWITCH. 

The stop on external interrupt switch (ECT-l) causes the data 
processor to stop upon the occurrence of an external interrupt, 
when in the "up" position and if the interrupt system is so enabled, 
The data processor stops displaying the PI and P2 interrupt param- 
eters in the A and B registers, just prior to entering the inter- 
rupt procedure. 



4-17 



NORMAL/CONTROL STATE SWITCHES. 

These are 2 position toggle switches which function to enable the 
stop switches to function when the data processor is in control 
state, normal state or both. 

PARITY SWITCH. 

This switch enables the processor to stop on a memory parity error. 

UNIT CLEAR SWITCH. 

The unit clear switch is a pushbutton type switch which functions 
to clear the flip-flops of the related data processor, when de- 
pressed . 

LOCAL/REMOTE SWITCH. 

This switch is a 2 position toggle switch which places the data 
processor to a local state, when placed in the "LOCAL" position. 
The processor unit functions normally when in the local state ex- 
cept for the following: 

a. The scan bus is isolated from the system functionally, 
so that manual intervention within the processor will 
not interfere with the rest of the system. 

b. The facilities of the "READ PROC REG" switches are 
enabled . 

AD J (0,0) SWITCH . 

This is a pushbutton switch which activates the Push Down Stack Reg- 
ister operator to cause all TOS registers to be stored in memory, 
therby saving the contents of the A and B registers so that these 
registers may be used to subsequently manipulate the data proces- 
sor's I.C. memory via the maintenance panel switches (READ-IC and 
WRITE- IC). The ADJ (0,0) switch is active only when the proces- 
sor's clock is enabled. 

READ IC SWITCH. 

This is a pushbutton switch which initiates a Read Processor Reg- 



4-li 



ister operator to read the contents of a processor IC memory reg- 
ister into the A register (19:20). The address of the selected IC 
memory register must be placed into the B register prior to de- 
pressing this switch. The "READ IC" switch is active only when 
the processor's clock is enabled. 

READ IC OPERATION. 

a. Adjust 0,0. 

b. Load the address in the B register. 

c . Turn BROF on . 

d. Depress the READ IC pushbutton; the contents of the 
addressed cell will appear in the A register. 

WRITE IC SWITCH. 

This switch is a pushbutton switch which activates a Set Proces- 
sor Register operator to cause the contents of a processor IC 
memory register to be replaced with the contents of the A register 
(19:20). The address of the selected IC memory register must be 
placed into the B register prior to depressing this switch. The 
"WRITE IC" switch is active only when the processor's clock is 
enabled. 

WRITE IC. 

a. Adjust 0,0. 

b. Load the address in the B register. 

c. Load the information to be written in the A register. 

d. Turn on AROP and BROF. 

e. Depress the WRITE IC pushbutton; the contents of the 
A register will be written in the cell addressed. 



4-19 



READ PROC REG SWITCHES. These switches enable the read out and 
display of the related processor register (iC memory register) . 
The register's contents are displayed only while the switch is de- 
pressed, releasing the switch allows the processor to revert to its 
prior state. The "READ PROC REG" switches activate a DC read out 
of the IC memory cells and as a result are enabled only when the 
processor is in "LOCAL". The "READ PROC REG" switches along with 
their functions are listed below: 

a. Switch S is the read S register switch. 

b. Switch F is the read F register switch. 

c. Switch PBR is the read PBR register switch. 

d. Switch PIR is the read PIR register switch. 

e. Switch BOSR is the read BOS register switch. 
P. Switch LOSR is the read LOS register switch. 

NOTE 

These IC memories are dis- 
played in the SM register. 



4-20 





■ 


8 


3 




/ BINARY 


4v//y/ 


4 


2 


DECODE FOR DESIRED 


/ WEIGHT 


2 5 


2 , 


REGISTER 


) 


' 4 


' 





= DISPLAY REG =) 15 

1 = DISPLAY REG 16 => 31 

2 = INDEX REG => 7 

3 = BASE REG => 7 



Register 

Name 

D00 
D31 

PIR 

SIR 

DIR 

TIR (BUF3) 

LOSR 

BOSR 

F 

BUF 

PBR 

SBR 

DBR 

TBR (BUF2) 

S 

SNR 

PDR 

TEMP 



Usage 



Display 

Program Index 

Source Index 

Destination Index 

Table Index 

Limit of Stack 

Base of Stack 

MSCW Address 

Used for Temporary Storage 

Program Base 

Source Base 

Destination Base 

Table Base 

Top of Stack Address 

Stack Number 

Program Segment Descriptor Index 

Temporary Storage 



Decimal 


Hexidecimal 


Address 


Address 


0=> 


00=> 


31 


IF 


32 


20 


33 


21 


3k 


22 


35 


23 


36 


2k 


37 


25 


38 


26 


39 


27 


k8 


30 


k9 


31 


50 


32 


51 


33 


52 


3k 


53 


35 


5h 


36 


55 


37 



Figure k- 5 . Address Register 



'4-- 21 



READ PROC REG 





^1 




F PBR 






ADJ-0.0 



PIR BOSR LOSR 

—STOP MODE— i 



CONDITIONAL 
HALT 





READ-IC 




WRITE-IC 




PARITY I NT- 1 



CONTROL EXT- 
STATE 



START NORMAL SECL 
ilAKI STATE 



LOCAL 




CLEAR 



REMOTE 



Figure k- 6. Panel E 

MULTIPLEXOR REGISTERS AND FLIP FLOPS. 

The MPX Registers and Flip Flops are displayed on Panel B as seen 
in figure k-7 , This panel is shared with the Processors for display- 
mode . 

ROW B. 

This row contains the logical elements for Maintenance Diagnostic 

Logic. Each flip flop may be used in one of two ways, I/O testing 

or Data Processor testing. 



4-22 



FLIP FLOP 

FECII 

AROF 

ESTF 

TNFF 

MA OF 

LPF 

CERF 

EPvRl 

ERR 2 

LOIF, L02F 

MAOl =) MAIO 

BOIF => B08F 

AOIF =) AlOF 



USE ON I/O TEST 

OFF FOR I/O 

NOT USED 

TAPE VERTICAL PARITY 

"TEST NOT" FLIP FLOP 

MEMORY ACCESS OBTAINED 

BAD RECORD MEMORY 

CONTROL PARITY ERROR 

SOLID ERROR 

INTERMITTENT ERROR 

SEQUENCE COUNT 

MEMORY ADDRESS 

TAPE READ CONTROL 

CHARACTER BUFFER WORD BUFFER 



USE ON DP TEST 

ON FOR DP 

A,C REGISTER OCCUPANCY 

END OF STRING FLIP FLOP 

"TEST NOT" FLIP FLOP 

MEMORY ACCESS OBTAINED 

MEMORY INFO PARITY BIT 

CONTROL PARITY ERROR 

SOLID ERROR 

INTERMITTENT ERROR 

SEQUENCE COUNT 

MEMORY ADDRESS 

DATA 

COMMAND- DATA 



ROW C. 

This row contains the 51-bit data register used in I/O operations 

along with the following control flip flops: 



PSYF - Processor Sync 

PSRF - Processor Scan Request 

SAOF - Scan Access Obtained 

MATF - Mark Access Time 

STEF - Scan Transmission Error 



Scan Bus Control Flip Flops 



ROW D. 

This row contains the 60-bit Command Register used in I/O operations 

Refer to figure k-7 for a detailed description of this register. 

ROW E. 

This row contains the 10 sets of Associative Tag Register flip flops 

used for Scratch Pad Memory assignment. Also within each set of 

flip flops is the corresponding Read Scratch Pad Memory (RSPM) flip 

flop. 

Row E also contains (5) MTRI flip flops, one for each pair of Tag 

registers . 



k-23 



ROW F. 

This row contains the following MPX Control flip flops: 



IC 1 =) 8 Initiate Count Cycle for operational 



sequence flow. 



KY 1 =) 5 Key Register flip flops used as comparitor selection of 
Scratch Pad Memory slots. 

LK 1 =) 5 Link Register used on initiate cycle for Key Register 
selection . 

Al =) A8 

Bl =) B8 Input Translator Digit Bits 

CI =) C8 

Dl => D8 

ESCF Enable service cycle 

EICF Enable initiate cycle 

RRDF Read result descriptor 

PCTF Service priority control 

RCDF Read SPM to Command data register 

MTOF Memory time zero 

AP2F Address plus 2 store 

LSAF Least significant address 

ROW G. 

This row contains the Time of Day Register and the Interrupt status 
bit flip flops. 

TIME OF DAY => 43 - This register contains 44 flip flops of 
which 36 are used for time-of-day. The other 6 are used when the 
entire register is being used during MTR logic card test. 

IS =) 9 - Interrupt status bits. 



4-24 



ROW 



© 0O O 

o 000 
o 00 o 
0000 



000 
000 
000 
000 



0000 
00 00 
0000 
0000 



0000 
0000 
0000 
0000 



ie-0-GH©- 

MAOF" 

OOOO 

*ROF LPF DISF 

o QOO 

ESTF CERF ERR| LOIF 

OOOO 

TNFF FECH ERR2 L02F 



OOOO 

o 

MA08 

O 

MA09 

o 



000 

MACK MA09 

OOO 

MAOS MAC* 

OOO 



MA02 MA05 MA08 



MAOS MAC* MA09 



MAOl MA04 MA07 
CORE ADDRESS 



o 

BOIF 

o 

B02F 

o 

B03I 

o 

B04F 



B03P 807F 



o 

B05F 

o 

BO6F 

o 

807 F 

o 

B08F 



-TEST CASE -I 



o 
o 

AOIF 

O 

A02F 

o 

A03F 



OOOOO 

C06F 



O O 

o o 
00 
00 

o 



OOOO 

A04F A07F AIOF C03F 

OOOO 

A05F A08F COIF O04F 

OOOO 

A06F A09F C02F C05F 

STRING 



o 

C07F 

o 



MDL DISPLAY- 



o 
o 
o 



OOO 

OOO 

OOO 
OOO 
OOO 
OOO 
OOO 
OOO 



©000000 

MATF 

o o 



OOOO 



SAOF 

o o 

PSRF 

© o 

STEP PSYF 



OO 

50 

OO 

49 

OO 



47 f44 41 

opol 

46 43 *Q J 

OlOjO 

45 42 39 



STEF PSYF DQ5I 46 45 42 

©-©-0 OOO 

III 107 103 99 9* 

OOOOOO 

HO 106 102 96 94 

OOOOOO 

109 10s 101 97 93 

©-©-0-0 o o 



o~o 



opa 

3« 35 r 32^ 

OOOO 

37 34 31 

ODO 

36 ^3 30 



OOOO 

"AJS"" 



OOOO © 



29 26 23 



J 23 ftb-' 17 
obd 



106 104 100 96 

ADDRESS 



o 
o 
o 



o 
o 
o 



OOOOOO 



OP' 

14 I ■ 

Oj 

13 I 




Qjor© 
r 9J9 



91 90 89 



OOOOOO 

87 86 85 84 83 82 

OOOOOO 

81 80 79 78 

OOOOOO 

.77 76 75 74 73 72 ,, 

I LENGTH 'I 



00000a 

71 1 1 56 54 

OOjOOj© o 

70 67 I 64 61 57 53 

OfOOQO O 

69 I 66 63 60 1 56 52 

olgooio © 

66 ^5 62 39^ 55 51. 



OOOO 



©-© 

RSPM 103 

o o 

105 102 

©-© 



o 
o 
© 



e 

O 

4 

o 

2 

o 



00 

RSPM 93 

OO 

95 92 

OO 



OOO 

MTRI 

OOO 

RSPM 

o 



-COMMAND REGISTER- 
TAG REGISTER 



06 

3 

OO 
OO 



RSPM 63 

o o 

65 82 

o o 



o 6 
o 6 
06 



75 

o 

1 



o 



65 62 

o o 



o o 



000000000000© 

"""■ MTRI 

o o 

RSPM 13 

OO 

45 42 

OO 



o 

73 

o 



o o 

RSPM 63 

o o 



00 

RSPM 53 

OO 

55 52 

OO 



665666 

RRDF 

OO OOO 

PCTF AP2F 

OO OOO 

RCDF LSAF 

OO OOO 



00 

RSPM 33 

OO 

35 32 

OO 



o 
o 

ESCF 

o 



6666 

06 C6 B6 A6 

OOOO 

04 C4 B4 A4 

OOOO 

D2 C2 82 A2 

OOOO 

Dl CI Bl Al 



00 

RSPM 23 

OO 

25 22 

OO 



OO 

15 12 

o o 



6666 

OOOO 
OOOO 
OOO© 



© 
o 



OOO 

7 3 

OOO 
©4©-©-© 
©-©-©-© 

Ottt) 
OOOO 
OOOO 
©OOO 



OOOOOO OOOO© OOOO© 

■ ' TIME OF DAY/ CARD TEST REGISTER 

OOO OOO OOOO 

29/11 26/IF 23/IC 20/OW 

o o 

22/0Y 19 /Ov 




00 

35/1P 32/1 L 

o o 

34/IN 31/IK 

0© 

_Q 3 3/IM 30Aj 27A> 



OO 

17/DT I4/0Q 

OO 

I6/0S I3/0P 



O© 

05/0G 02/00 

OOO OOOOOO ( 

28/IH 2S/IE 22/0Y 19/DV I6/0S I3/0P 10/OL 07^01 04/OF Ol/OC 

9 Q. 



?99 

/ou 15/bf? 12/0N 



OO 

ll/OM 08/0J 

OQ 

10/OL 0770J 



'SgB i2£or 



5117 SII3 S107 RDAB 



OO OOOOOOO 

SH6 Stl2 SI06 ADP2 

00 oooooo© 

SII5 Sill MINS SKI 

OO OOOOOOO 



SI 14 SI 10 SAL IOCB 



OOOO 

ANXF SIPL 

OOOO 

MAOF SPEL 

° QQ ® 

MTOF Stf2 MIPL 

OOO© 

MANF CRF MAPL 



H 



Figure 4-7 • Panel B 



4-25 



ROW H. 

This row contains the following control flip flops: 

MAPL - Memory address parity error level. 

MIPL - Memory information parity error. 

SPEL - Scan parity error. 

SIPL - Scan bus information parity. 

CRF - Clear Flip Flop. 

SIF2 - Scan In Flip Flop. 

MANF - Memory access needed. 

MROF - Memory read obtained. 

MAOF - Memory access obtained. 

ANXF - Allow Next Service Cycle Control. 

IOCB - Input/Output Complete Bus. 

STCB - Start Channel Bus. 

ADP2 - Address Even Bus. 

RDAB - Result Descriptor Available Bus. 

LSAL - Least Significant Address. 

MINS - Minus Bus Level 

SI06 =) SI07 

MPX MAINTENANCE CONTROL PANEL. 

Panel D as seen in figure 4-8 is used for local maintenance opera- 
tions with the Multiplexor. Four types of operations can be accom- 
plished using this panel: 

a. Reading and writing the MPX scratch pad memory. 

b. Reading and writing main memory. 

c. Executing I/O descriptors. 

d. Logic Card testing. 

The requirements for these operations are twofold; the MPX must be 
in local using the Local/Remote switch, the MPX display mode must 
be active as well as system clock. 

The following paragraphs will deal with the operational use of these 
maintenance switches to accomplish the above 4 modes. 



4-26 



WRITE SPM. 

Single or Continuous writing into a SPM location addressed by the 

tag word is accomplished as follows: 

a. Put MPX in Local mode. 

b. Scan- in Tag word in the Tag Reg. 

c. Scan- in the same Tag word into the Key Reg. 

d. Scan- in the desired contents into the Command and Data 
Registers (112 bits). 

e. Put Read/Write switch on the MPX maintenance control panel 
to the WRITE position. 

f . Put Memory/SPM switch on the MPX maintenance control panel 
to the SPM position. 

g. Activate Maintenance Mem/SPM Enable switch on the MPX 
maintenance control panel. 

h. II single cycle operation is desired, press Start button 
for each SPM write cycle. 

i. If continuous recycling is desired, activate the Recycle 
switch and press Start button to commence recycling. 

j. To stop recycling, place Recycle switch to OFF position. 

READ SPM. 

Single or Continuous reading of a SPM location is accomplished the 

same as writing except for 2 steps. 

Step k - Omit 

Step 5 - Put the Read/Write switch to the READ position and 
proceed as in WRITE SPM mode. 



k-Z] 



WRITE MAIN MEMORY. 

Single words can be written to main memory from the Data Register 

in the following manner: 

a. Put MPX in Local mode. 

b. Scan- in Memory Address into Command Reg. 

c. Scan- in any desired bit pattern into the Data Reg. (Pattern 
will not clear out of the Data Reg. after each write op- 
eration . ) 

d. Put Read/Write switch on the MPX maintenance control panel 
to the WRITE position. 

e. Put Memory/SPM switch on the MPX maintenance control panel 
to the MEM position. 

f. Activate Maint. Mem/SPM Enable switch. 

g. Press Start button for each memory write cycle. 

NOTE 

Activating Memory Request 

Inhibit switch will disable 

all logic that might set 

MANF including local maintenance. 

READ MAIN MEMORY. 

Main memory cells may be read either singly or continuously from 

one address or consecutive addresses in the following manner: 

a. Put MPX in Local mode. 

b. Scan- in Memory Address into Command Reg. 

c. If recycle, use "Write SPM" maintenance logic to write 
Command/Data Reg. into SPM (highest priority TAG Word with 
zeros . ) 



4-28 



d. Put Read/Write switch, on the MPX maintenance control panel 
to the READ position. 



e . 



Put Memory/SPM switch on the MPX maintenance control panel 
to the MEM position. 



f. Activate Maint . Mem/SPM Enable switch 



g 



If single read cycle operation is desired, press Start 
button for each memory read cycle. 



h. If continuous recycling is desired, activate the Recycle 
switch and press Start button to commence recycling. 

i. To manually stop recycling place Recycle switch in OFF 
position. 

j. If stop on error is desired during recycling, activate the 
Error Stop switch. If a memory parity error or time out 
occurs, recycling will stop with the Error flip-flop set. 
Pressing the Start button will clear the error and restart 
the cycling. 

k. Note that activating Memory Request Inhibit switch will 
disable all logic that might set MANF including local 
maintenance. 

1. Activating the Inhibit Memory Address Count switch, if so 
desired, will cause retention of the original memory ad- 
dress with each cycle. Otherwise, the memory address will 
be updated with each memory cycle. 

EXECUTING I/O DESCRIPTORS. 

SINGLE CYCLE. A single execution of an I/O descriptor found in the 

Command/Data register is defined below: 

a. Put MPX in Local mode. 



h-29 



b. Scan- in Area and I/O Descriptors into Command/Data Reg- 
isters. The specified Unit Designate wili select the chan- 
nel on which the descriptor is to be executed. 

c. Utilize single "Write SPM" procedure for any SPM location 
using a code of 00001 in Key and Tag Registers. 

NOTE 

There must be at least 
one other Tag word avail- 
able at the beginning 
of the test. 

d. Place Maintenance Mem/SPM Enable switch in OFF position. 

e. Place Maintenance Descriptor Enable switch in ENABLE posi- 
tion . 

f . Press Start Button once to execute a single maintenance 
descriptor once for each depression of the Start button. 

RECYCLE. Continuous executions of I/O descriptor found in the Com- 
mand Data Register are accomplished as follows: 

a. Steps 1 through 5 are the same as Maintenance Descriptor 
(single) procedure. 

b. Activate Recycle switch. 

c. Press Start button to commence recycling of the same main- 
tenance descriptor. A new cycle will be intitiated upon 
completion of the previous I/O operations defined by the 
maintenance descriptor. 

d. To manually stop recycling place Recycle switch to OFF 
position . 



^-30 



e . 



If stop on error is desired during recycling activate 
the Error Stop switch. Upon detection of a 'result des- 
criptor error from the P.C. or an error in initiating the 
channel, recycling will slop with the Error flip-flop set. 
Pressing the Start button will clear the error and restart 
the cycling. 



ENABLE 



CARD TEST 



START 



OFF OFF 

•MEM INHIBIT 



REQUEST ADRS-COUNT 



NORMAL 



NORMAL 



MAI NT DESCRIPTOR 
ENABLE 



OFF 



o o o 

IMCF RECF ERRF 

RECYCLE ERROR STOP 




START OFF OFF 

MA I NT MEM/SPM 

ENABLE MEM WRITE 



OFF 



SPM READ 



UNIT 



LOCAL 




CLEAR 



REMOTE 



Figure 4-8. Panel D MPX Control Panel 



4-31 



LOGIC CARD TESTING. 

Logic Card testing is accomplished by using a MDL test case tape, 
the Time of Day (TOD) register and a special single card slot lo- 
cated on the MPX backplane. The testing procedure is activated by 
putting the card test enable switch up, loading the TOD with the 
appropriate test code and activating the card test start switch. 
The output of the card under test will be displayed in the hh flip 
flops that represent the TOD register. 

OPERATORS CONTROL CONSOLE. 



The Operators Control Console as seen in figure 4-9 contains an 
operators panel and a visual message control center for communica- 
ting with the Operating system. A total of 8 devices, such as In- 
put Display or TC 5°0> may be used for this communication. 

OPERATOR PANEL. 

The operator panel includes the following switches and indicators. 

POWER ON (Switch Indicator, White). This Switch/indicator initiates 
the power on cycle for all Central System units. The indicator is 
lit and remains lit as long as power remains on. 

NOTE 

a. The peripheral units power must 
be turned on and off at each 
peripheral unit. 

b. When power is turned on, Disk 
Load is selected. 

POWER OFF (Switch, Brown). This switch initiates the power off 
cycle for all Central System units. 

HALT ( Switch/indicator , Red). Halt the system stopping all I/O 
operations in an orderly manner. The indicator is lit when all 
processors have been halted. 



4-32 



RUNNING (indicator, Yellow). This indicator is lit when the system 
is running. The run state is established by 2 second run multi ' s 
in each processor. Each processor multi is triggered by that pro- 
cessor executing an interrogate peripheral unit status operator. 
The run indicator is lit when the multi in any processor which is in 
remote is ON. If all processors are in local, the run indicator 
will also be lit. 

LOAD SELECT ( Switch/indicator , Yellow). This switch selects between 
Disk Load and Card Load. Each time the switch is depressed, the 
selection is changed. The indicator is lit when Card Load is se- 
lected. 

LOAD (Switch, Brown). The Load button is used to perform a load 
operation of the system. Two types of load can be performed as 
follows : 

Card Load Operation. 

The Card Load operation is used for initiating the system via the 
card reader. This type of initiation is used for reading a cold 
start deck or test routine decks. The following actions occur when 
the button is depressed and then released: 

a. The load timer in the Processor interrupt controller is 
triggered to produce an 800 nanosecond (LSIG) signal 
which is sent to MPX-A. 

b. Address registers LOSR, BOSR, F, STKNR, and Display are 
set to Zero. 

c. Register S is set to 8192. 

d. PDR (Program Dictionary Index) is set to a value of k. 

e. PIR (Program Index Register) is set to a value of 1. 

f . The Processor is forced into an idle state to await an ex- 
pected I/O finished interrupt. 



4-33 



g. g. The MPX responds to the LOAD signal by jamming the appro- 
priate unit number into the Command/Data register. The 

MPX sequence control logic is set to IC 02 and the card 
read cycle is started. 

h. The information (a bootstrap program) on the EBCDIC punched 
card is read into the 1st twelve memory locations. This 
information must contain tag fields (6 chr/wd plus tag). 

i. At the end of the successful card read, the MPX sends an 
I/O finished interrupt to the Processor. It responds by 
entering a hardward interrupt handling procedure. Memory 
cell DO 3 (absolute cell 003) contains a portion of the 
bootstrap program that is subsequently used to handle the 
interrupt and then causes the remaining card deck to be 
loaded . 

Disk Load Operation. 

The Disk Load operation is used for initiating the system by reading 
8192 words from the 1st segments of disk memory. This type of an 
operation is used to bring the 1st portion of the operating system 
to core memory. 

The same hardward functions take place as for card read except for 
two things; 

a. A disk unit number is placed in the Command/Data register 
because the Load select switch selected a DISK LOAD. 

b. The I/O finished interrupt reflects a disk operation in- 
stead of a card operation. 

VISUAL MESSAGE CONTROL CENTER (Refer to Figure 4-10). 
The Visual Message Control Center consists of one or more Input 
Display Modules each of which contains an input keyboard and a 
video output screen. 



4-34 




Figure 4-9. Operators Control Console 



4-35 




Figure 4-10. Visual Message Control Cent 



;er 



KEYBOARD CONTROL KEYS. 

The following is a list of the keyboard control keys and their func 

tion. Refer to figure 4-11. 



Key 



Function 



LOC 



Places the system in the Local Mode, which 
lights the Local indicator. 



REC 



Places the system in the Receive Mode, which 
lights the Receive indicator. 



XMIT 



Places the system in the Transmit Mode, which 
lights the Transmit indicator. 



4-36 



Key 
PRINT 



X ETX 



C> us 



<3 RS 



\ HOME 



Function 

Causes the printer mode to be entered. This 
mode causes the Transmit light to blink. Re- 
turns to Local Mode on completion of the print. 

End of text character. Places the end of text 
character at the cursor location. 

a. Shifted - Places the system into the form 
compose mode and blinks the Local light. 

b. Unshifted - Takes the system out of the form 
compose mode. 

Shift-In - Places a Shift-In (Si) character at 
the cursor location if the system is in the Form 
Compose Mode. 

Shift-Out - Places a Shift-Out (SO) character 
at the cursor location if the system is in the 
Form Compose Mode. 

Causes the cursor to be moved to the home (upper 
left) position. 



LINE ERASE 



a. If the system does not have forms option, or 
if it is in the Form Compose Mode, Line 
Erase erases all data in the line except 
tab flags. Data is erased from the cursor 
position (including the cursor position) up 
to and including the last character in the 
line . 

b. If the system has Forms Options and is not 
in the Form Compose mode, Line Erase erases 
all data (except tab flags) that are not 
bracketed by Shif t-In/Shif t-Out . 



^-37 



Key 

LINE ERASE 
(cont ) 



\ CLEAR 



ERASE LOCK 



TAB 



TAB CLEAR 



1 (Line Feed) 



Func tion 

c. Line Erase will not function unless Erase 
Lock is depressed simultaneously with Line 
Erase . 

a. Unshifted - Clear erases all data on the 
screen except tab flags and with Forms 
Option data bracketed by Shift- In/Shift- Out 

b. Shifted - Clear erases all data on the 
screen and all tab flags. 

c. Clear will not function unless Erase Lock 
is depressed at the same time as Clear. 

Erase Lock is used as an interlock for Clear 
and Line Erase. Erase Lock must be depressed 
to permit operation of the Clear or Line Erase. 

a. Unshifted - Tab causes the cursor to move 
forward to the next tab stop location. If 
no tab stop is found on a line, the cursor 
moves to the left edge of the next line. 

b. Shifted - Shifted Tab is Tab Set. Tab Set 
causes a tab stop flag to be entered at the 
cursor position in all lines. 

a. Unshifted - Tab Clear causes the removal of 
the tab stop flag located at the cursor 
position in all lines. 

Line Feed moves the cursor down one line. When 
the cursor is in the bottom line, L.F. causes 
it to reappear in the top line. 



4-38 



T (Reverse Line Feed) 



(Backspace ) 



(Forward Space) 



REPT 



Reverse Line Feed moves the cursor 
up one line. When the "cursor is in 
the top line, RLF causes it to reap- 
pear in the bottom line. 

Backspace cursor one character. When 
the cursor is at left edge of page, 
B.S. causes it to reappear at right 
edge of page in the same line. 

Forward Space moves the cursor one 
space to the right. If the cursor is 
at right edge of page, F.S. causes it 
to reappear at the left edge down 
shifted one line. If the cursor is 
located in last position of bottom 
line, F.S. causes it to reappear in 
the Home position. 

If the Repeat key (REPT) is depressed 
along with any other key except LOC , 
REC, XMIT, TAB CLEAR or CLEAR, that 
key will be repeated at a rate of 
about 15 Hertz. Depressed in conjunc- 
tion with LOC, REC, XMIT, TAB CLEAR 
or CLEAR Repeat has no effect. 



h-39 



XMIT 


ETX 
X 


ERROR 
RESET 


REPT 


LOC 


FORM 


REC 


RS 
< 


PRINT 


US 



> 

1 


2 


# 

3 


$ 
4 


% 

5 


& 
6 


< 

7 


( 
8 


) 1 ERASE 
9 1 jrf 


= 


BACK 
SPACE 






Q 


W 


E 


R 


T 


Y 


U 


1 


O 


@ 

P 


* 


CR 
V 






A 


S 


D 


F 


G 


H 


J 


L" 
K 


X 

L 


+ 

i 


A 






SHIFT 


z 


X 


C 


V 


B 


N 


M 


< 

» 


> 


? 
/ 


SHIFT 










SPACE BAR 









HOME 


CLEAR 


LINE 
ERASE 


ERASE 
LOCK 


TAB 


TAB 
CLEAR 


' 


' 


t 


— 


»■ 



Figure 4-11. Keyboard Format 



MEMORY TESTER. 



The B 6500 includes a Memory Tester for diagnosing and testing any 
of the Memory modules attached to the system. 




Figure 4-12. Memory Tester 

The Memory tester is located in a small cabinet, with its display 

panel as shown in figure 4-12. The tester can be used in 2 modes, 
Non-Test or Test (figure 4-13). 



4-40 



NON-TEST. 

Three types of* operations: 



a 



Single cycle read or read/write. 



b. Search memory(s) for specific data; search for equal or 
unequal . 

c. Sample a given address for changes. 

TEST. 

The following operations performed using the test pattern switches: 

a. None of the patterns selected checks for parity errors 
using the read only operation. 

b. #1 Test-pattern selected enables a fixed test pattern. 

c. #2 Test-pattern selected runs an all "one" test. 

d. #3 Test-pattern selected runs an all "zero" test. 

e . #4 Test-pattern selected runs a checkerboard pattern 
writing two zeros then two ones. 

f. #5 Test-pattern selected runs the checkerboard complement 
pattern test. 

g. #6 Test-pattern selected runs the bit complement pattern 
test . 

h. #7 Test-pattern selected runs the complement bit complement 
pattern test. 

i. #8 Test-pattern selected runs the full walking "one" pat- 
tern floating one test. 

j. #9 Test-pattern selected runs the full walking "zero" pat- 
tern floating zero test. 

k. #12 Test-pattern selected runs the memory clear pattern ?= 
Master reset test. 

^-41 



MEMORY TEST PANEL- 



START 



NOT EQUAL [-SEARCH INHIBIT 

^ 4qT ^NORMAL Q ^ ^ ^ ^ ^ 

HALT EQUAL SAMPLE HALTERR/CHGE BIT^RESET WORD^^ROTECTED O'RIdTpROTECT WRITTrEQUEST CLEAR 



i COMPARE/READ/LOCKOUT- 



COMPARE 



™£ T © ©©©©©©©©©©©©©© 



50 47 44 41 38 35 32 29 26 23 20 



49 46 43 40 37 34 



28 25 22 19 



7 14 

c 

16 T3 



10 



51 48 45 42 39 36 33 30 27 24 21 18 

mmmim^ammm—mm—mmmmmmmm—m—mmmmmmmmm—mim—^m MEMORY WRITE"— ■— ■■— 



©©©©©©© 



WRITE CLEAR 50 47 44 41 38 35 32 29 26 23 20 17 

©©©©©©©©©©©©©©©©© 

49 46 43 40 37 34 31 28 25 2Z 19 16 13 10 7 4 I 

©©©©©©©©©©©©©©©©© 

51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 O 

■ MODULE ADDRESS — — ■™"™"™ ■■— ■■ WORD ADDRESS —■—■■- 



1 n 



MEM NOT READY MEM ERROR PARITY ERROR COMPARE MONITOR 



ADRS CLEAR 19 16 



u 

5 2 



n; 



CYCLE CONTROL- 



TEST CONTROL- 



WRITE 



I BIT 0-25 I §£& I 



18 15 



MRQF MABF MAOF 

'TIME COUNTER ■ PHASE ■ 



SINGLE I BIT 0-25 
>FV)LL 
W T ^ STACK 

COMPLETE tU BIT 26-51 NORM 17 14 



MICR 



REQUEST DELAY* 



' MODULE LOCK* 




12 9 6 3 

i«i™— ■- ■ WORD LOCK ■■■■■■ 



#99 



NORM 




NONTEST 



© 



>ALL"I 



>ALL-0 



. CHK'BD COMPL 



1 BIT COMPLEMENT 



COMPL- BIT COMPL 



FULL WALK'S- I 



>FULL WALK'G-O 



WALK'G-I 



WALK'G-0 



MEM CLEAR 



TEST ON 



Figure 4-13. Memory Tester Panel 



h-kz 



SECTION 5 
SYSTEM CONCEPT 



GENERAL . 



The B 6500 system consists of one or more Processors , one or more 
I/O multiplexors, Main Memory, a Memory Tester, one or more Power 
modules, an Operators Console, a Maintenance Diagnostic Processor, 
a Display Panel, one to four Peripheral Control cabinets and the 
associated Peripheral equipment for Input/Output. This section 
generally defines the overall system hardware operation. 

PROCESSOR . 

The Processor produces the objective results of a program by per- 
forming the necessary arithmetic and logical functions of the pro- 
gram flow. 

The Processor contains two major divisions: the Functional Re- 
sources and Operator Algorithms (figure 5-l). The Functional Re- 
sources are referred to as the "hardcore" of the Processor. 

OPERATOR FAMILIES. 

The Functional Resources are the Arithmetic Unit, Data Registers, 
Address Processor Unit and Seven Functional Controllers. The op- 
erator algorithms provide the logic required to control the func- 
tional flow of the program. The ten groups of these operators are 
called the Operator Family Controllers. 

The Operator Family Controllers and Functional Controllers are 
linked by 13 busses (ZO through Z12). These busses provide for 
data movement and signal routing within the processor (figure 5-2). 

A bus is a group of wires used to transmit signals from one place 
to another. The busses within the transfer controller are etched 
on a single card connecting the same bit of all "hard registers" 
together, i.e. , Bit 1 of Registers A, B, C, X and Y are all on the 
same physical card. 



5-1 



FUNCTIONAL RESOURCES 



OPERATOR ALGORITHMS 



ARITHMETIC 

UNIT 

(48 BIT ADDER) 



ADDRESS 

PROC UNIT 

(960 BIT I.C. 

MEMORY & 20 

BIT ADDER) 



DATA REGISTERS 

(A, B, C, X, YANDP 

51 BITS EACH) 



MEMORY 
CONTROLLER 



PROGRAM 

SEQUENCE 

CONTROLLER 



STACK 

ADJUST 

CONTROLLER 



INTERRUPT 
CONTROLLER 



OP. FAMILY 
CONTROLLER - A 



OP. FAMILY 
CONTROLLER - B 



OP. FAMILY 
CONTROLLER - C 



OP. FAMILY 
CONTROLLER - D 



OP. FAMILY 
CONTROLLER - E 



OP FAMILY 
CONTROLLER - F 



OP. FAMILY 
CONTROLLER -G 



OP. FAMILY 
CONTROLLER - H 



OP. FAMILY 
CONTROLLER - I 



OP. FAMILY 
CONTROLLER - J 



ARITHMETIC 
CONTROLLER 



STRING 

OPERATOR 

CONTROLLER 



TRANSFER 
CONTROLLER 



Figure 5-1. B 65OO Processor Organizatio 



n 



The operators are grouped into ten groups called the Operator Fam- 
ilies (figure 5-1). The grouping of related operators into families 
minimizes the logic required in the processor. The Ten families of 
operators with a brief purpose for each are: 



a. Family A OPS 

b. Family B OPS 

c. Family C OPS 

d. Family D OPS 

e. Family E OPS 

f. Family F,G,H, OPS 

g. Family J OPS 
h. Family K OPS 



Arithmetic Operators 

Logical Operators 

Sub-routine Operators 

B 65OO Word Oriented Operators 

Scaling Operators 

String Operators 

Value Call 

Name Call 



PROGRAM CONTROLLER (Refer to Figure 5-2). This controller controls 
the program flow in the following manner: first, it controls the 
transfer of a program word to the P register via the Memory Control- 
ler and Z3 bus in the Transfer Controller. This word contains six 
8-bit instruction syllables. It also selects and decodes the syl- 
lable to be executed, and furnishes this OP code to all the Family 
Controllers thru the Z10 bus. The Program controller strobes the 
proper OP family allowing that OP family to proceed thru its logical 



5-2 



steps performing the function of that operator. At the completion 
of the operator a SECL (syllable execute complete level) is sensed 
by the Program Controller which then decodes the next syllable of 
the P register. 

TRANSFER CONTROLLER (Refer to figure 5-2). The Transfer Controller 
has two major sections: a hard register section, referred to as 
stack registers, for data and program information, and an internal 
data transfer section. Six busses, Zl thru Z6, are used for the 
normal data movement to and from the hard registers. Zl, Z2 and 
Z3 are input busses to these registers and Zk , Z5 and Z6 are output 
busses. The capacity of each bus is 51 bits. 

Two special busses are used for arithmetic operations. Z7 is used 
for transferring data from the A, B or Y registers to the AA reg- 
ister of the high speed adder. ZO is used for transferring data 
from the CC register of the high speed adder to the B, C or Y reg- 
isters as shown in figure 5-5 • 

Stack Registers. 

Each information register has 51 bit positions. Registers A, B, C, 
X and Y are for information handling during program flow. Register 
P contains one B 6500 program word. The P register contents are 
never written into Main Memory. 

The Z3 and Zk busses provide for bi-directional data flow between 
the hard registers and Main Memory or the Multiplexor. 

The A and B registers are the Top of Stack registers, while X and Y 
are normally second-word information registers for double- precision 
operands. Register C is a general purpose register which provides 
temporary storage during syllable execution. 

Internal Data Transfer Section (Refer to figure 5-3). 

The internal transfer section permits the following data transfers 

between stack registers: 



5-3 







Q£ 


o 


o 


LU 

_l 
1 


z 


t— 

2 


o 

as 


t— 


o_ 


z 




O O 






u 






i/i 


CXL 


D 


_J 


CO 


~ ^ 


o 


O Q 


*~ 


~R 


NJ 


O Q 


N. 


> 


X 


5^ 




23 




o & 




ac *— ' 




O. 





o 
z 4 



o 
5 



s 

to 
nJ 
■H 
A 

o 
o 

H 

m 

o 

(ft 
Cfi 
CD 
O 
O 

u 

Ph 

o 
o 

in 
vo 

PQ 



CM 

i 

CD 
U 

to 
•H 



5-^ 



a. A direct, full-word transfer path using the Z5 and Z2 
busses . 

b. A logical transfer path to create the results of the Fam- 
ily B (logical) operators, using the Zk and Z3 busses. The 
logical transfer path also provides one additional full 
word transfer path between registers. 

c. A steering Network and Mask network providing a field dis- 
placement between stack registers using the Z6 and Zl 
busses . 

d. An Insert Matrix providing character-handling operators 
with the ability to store into any of the k, 6 or 8-bit 
fields using the Z5 and Z1 busses. 

e. A transfer path to the address adder of MEMORY/MPX Control- 
ler via the Z6 to Z8 or Z9 busses. This path extracts one 
of four fields, (39:20), (35:16), (19:20) or (13:14), 

from a stack register during execution of operator syllables 

f . A data movement path to and from the high speed adder via 
the Z0 and Z7 busses. 

Mask and Steering. 

The mask and steering network moves bit fields from register to reg- 
ister, via the Z6 and Zl busses. All bits are transferred to and 
from the busses in parallel. Two pointers set up a "window" de- 
fining the upper and lower limit of the bits being transferred to 
the accepting data register. A displacement register shifts the 
bits to the right, to k7 bits from the position previously held 
in the sending data register.. The three controls used to steer and 
mask are : 

a. TOA (TOP OF APERATURE) - the highest bit position of the 
accepting field (highest bit of the window). 



5-5 



b. TOM (TOP OF MASK) - the highest bit position to be inhibi- 
ted on the transfer (lowest bit of the window). 

c. DIS (DISPLACEMENT) - a right shift of the bits through the 
steering matrix. 

The registers TOA, TOM, and DIS are set by the operator families or 
other controllers. 

Mask and Steering Example. 

Assume the C register contains a stuffed indirect reference word 
(SIRW) and it is necessary to extract the STKNR (stack number) field 
(bits 45:10) and place these bits into the INDEX field of the C 
register. The logic sets the window TOA := 29, TOM := 19, as shown 
in figure 5-4. The displacement register is set to 16: DIS := 16. 
The actual starting bit of the field is calculated as: TOA + DIS = 
29 + 16 = 45. 

All Bits in the C register are gated to the Z6 bus. The bits (ex- 
cept tag) are then shifted 16 places to the right with only the bits 
that align with the window appearing on the Zl bus. The Zl bus is 
then gated to the C register with the masked fields destroyed or 
retained depending on the operation performed. 

ARITHMETIC CONTROLLER (Refer to figure 5-2). The Arithmetic Control- 
ler is a Functional Controller between the Stack Registers (A, B, C, 
X and Y) and the Mantissa Adder. This Controller is enabled by the 
Arithmetic Family Operators and other operator families that re- 
quire the use of these facilities. 

High Speed Adder. 

Figure 5-5 depicts the logical flow of data to and from the high 
speed adder. The adder is made up of three 48-bit registers AA , 
BB , and CC and the associated add logic. The add logic receives 
its input from the AA and BB registers. The add logic output is 
fed into the CC register which feeds either the BB register or the 
hard registers via the ZO bus. 



5-6 



INSERT 




Zl 



MASK 
NETWORK 



H2 



ZO 



K 



^ 



V 



V 



V 



23 



^. 



^ 



^ 






X 



^ 



K 



^ 



L\. 



V 



4 BIT (PACKED NUMERIC) 
6 BIT (BCL) 

8 BIT (EBCDIC) 



STEERING 
NETWORK 



DIRECT TRANSFER 
NETWORK 



LOGICAL TRANSFER 
NETWORK 



HIGH 
SPEED 
ADDER 



24 



A 



27 



A 



A 



A 



A 



A 



A 



A 



A 



25 



A 



A 



26 



ADDRESS 
ADDER 



26 
TO 
28 
OR 
29 
CONTROL! 



MEMORY 
INTERFACE 



Figure 5-3. Internal Data Transfer Section 



5-7 



45 



36 



STKNR 



ill 



C REG 



Z6 BUS 



t 11 



STEERING (DIS = 16) 




MASK 



t 1 II 



MASK 



Zl BUS 



29 



20 



C REG 



STKNR 



Figure 5-^. Mask and Steering 

INTERRUPT CONTROLLER (Refer to figure 5-2). The Interrupt Control- 
ler provides a method intervening in the program flow when a pre- 
determined condition arises. 

This controller sets up the necessary control words in the stack for 
entry into the Interrupt-handling procedure. Two identifying words 
are placed in the stack by the operator or the Interrupt controller. 



5-8 



Internal interrupts are divided into two groups, operator dependent 
and operator independent interrupts. 

The operator dependent interrupts are divided into two classes. Bit 
2k of the interrupt ID identifies the interrupt as class 1, where 
the values of PIR, PSR, PBR and PDR are "consistent". Bit 23 iden- 
tifies class 2 interrupts where the values were changed by the op- 
erator before the interrupt. 



ADDER 





s 


TACK REGISTER 


S 




Z7 


A 
R 
1 

T 
H 
M 
E 
T 
1 
C 

C 
O 
N 
T 
R 
O 
L 
L 
E 
R 


1 
















1 
1 


AA 

R 
E 
G 




ADD 
LOGIC 










REGC 




















BUS 
ZO 


1 
I 
















CC 

R 
E 
G 
1 

S 
T 
E 
R 






REG A 












1 










REG B 


1 
















I 

I 






1 

1 


BB 

R 
E 
G 






REG X 










I 
1 








REG Y 












1 
1 

1 














BUS 


1 

l 

1 


















1 





J 



Figure 5~5* Arithmetic Control 

O perator Dependent Interrupts . 

These interrupt conditions are sensed by the operator and normally 
results in a premature termination of the operator under control of 
the operator's own logic. The operator inserts both PI and P2 para- 
meters into the TOS and activates the interrupt controller. PIR and 



5-9 



PSR are reset to the beginning of the current operator before the 
interrupt, thus the operator is restarted upon return to the in- 
terrupted procedure. 

The operator-dependent interrupts are: 

a. Memory Protect 

b. Invalid Operand 

c. Divide by Zero 

d. Exponent Overflow 

e. Exponent Underflow 

f . Invalid Index 

g. Integer Overflow 
h. Bottom of Stack 
i. Presence Bit 

j. Sequence Error 

k. Segmented Array 

1. Programed Operator 

Memory Protect. 

This interrupt occurs when: 

a. A STORE, OVERWRITE, or READ/LOCK is attempted using a Data 
Descriptor that has the read only bit on (bit 43). The op- 
eration is terminated prior to the memory access, leaving 
the descriptor in the A register. 

b. A STORE is attempted into a word in memory that has a tag 
field representing PROGRAM CODE, RCW , MSCW , or SEGMENT 
DESCRIPTOR. The memory write is aborted when bit 48 is 
detected in the "flashback" word that is placed into the 
C register. The operation is terminated leaving the 
original addressing word in the A register. 



24 BIT 



X X 



Memory Protect Interrupt ID 



5-10 



Invalid Operand. 

This interrupt occurs when operators attempt to use the wrong types 
of control words or data. When control words and data are accessed, 
they are checked to meet the necessary requirements of the operator 
being executed. When the interrupt occurs, the operator is termi- 
nated prematurely. 



24 



BIT 





X 




X 





Invalid Operand Interrupt ID 

Divide by Zero. 

This interrupt results when a division operator is attempted with 

the divisor equal to zero. This interrupt terminates the operation 

prematurely, leaves the A register cleared, the interrupt ID in the 

B register and PSR and PIR backed up to point to the initiating 

operator. 



24 



BIT 

I] 



Divide by Zero Interrupt ID 

Exponent Overflow and Underflow. 

These interrupts occur when the capacity of the exponent field is 
exceeded for either single or double-precision arithmetic results 
The interrupt ID is dependent on the exponent sign and both clear 
the A register. 



24 



U 



BIT 



Exponent Overflow Interrupt ID 



5-11 



24 



[JIT 





X 




X 





Exponent Underflow Interrupt ID 



Invalid Index. 

This interrupt is caused by an attempt to index by less than zero 

or not less than the upper bound (length) in the operations: 

Family 



a. 
b. 
c . 
d. 

e . 

f . 

g. 
h. 
i . 



Occurs Index (A) 

Link List Lookup (b) 

Index (w 

Move Stack (C) 

Display Update (c) 

Dynamic Branch (C) 

Stuffed IRW (pseudo) (c) 

Index and Load Name (c) 

Index and Load Value (c) 



If an index outside the prescribed bound is attempted, the operator 
is terminated. Backing up PSR, PIR is only done on the first two 
operators . 



24 23 



ZT 



BIT 
= ON 
OR OFF 



Invalid Index Interrupt ID 

NOTE 

If bit 23 is on, 
bit 2k is off. 



5-12 



Integer Overflow. 

This interrupt occurs upon detection of attempted uses of operands 
greater than integer maximum value by operators that require inte- 
gers. In general, the checking is performed before the operand is 
converted into an integer by reducing the exponent field. The fol- 
lowing operators may invoke this interrupt. 

a. Integer Divide (both SP and DP) 

b. Integerize Truncated 

c. Integerize Rounded 

d. Occurs Index 

e. Integerize Rounded, Double Precision 

If the interrupt is invoked, the operator is terminated. 



24 



BIT 



3 



Integer Overflow Interrupt ID 

Bottom of Stack. 

This interrupt is used to inform the Operating System that a RETURN 
or EXIT Operator has caused the program stack to be cut back to its 
base. If the condition arises, the operator will terminate with the 
last accessed RCW (Return Control Word) left in the A register. 



24 



BIT 





X 




X 





Bottom of Stack Interrupt ID 

Presence Bit. 

This interrupt is used to inform the system that an attempt has been 
made to access a quantity not present in main memory. All operators 
that access memory with descriptors have the ability to set this 
interrupt. Special consideration is given to this type of an in- 
terrupt for data or procedure-dependent descriptors. 



5-13 



46 24 23 



O 



BIT 

O (? ON 
OR OFF 



Presence Bit Interrupt ID 

Special Consideration- Presence Bit Interrupts. 

There are two classes of presence bit interrupt conditions. 

a. Data Dependent 

b. Procedure Dependent 

Each class requires that the PIR and PSR value for the RC¥ be man- 
ipulated differently. 

Data-Dependent Presence Bit. The Data-Dependent Presence Bit In- 
terrupts are incurred while the processor is seeking data from with- 
in its current procedural environment. Recovery is achieved by re- 
executing the operator upon return from the "P-bit" interrupt- han- 
dling procedure. 

The P-bit procedure makes the non- present reference present prior 
to returning to the interrupted program. The PIR and PSR setting 
for the current operator are saved in the RC¥ for data-dependent 
presence-bit interrupts. 

Procedure-Dependent Presence Bit. The Procedure-Dependent Presence 
Bit Interrupts are incurred when the processor attempts to enter a 
new procedural environment or to return to an old procedure. These 
interrupts occur during display up-date and when trying to "digest" 
a non-present segment descriptor. Recovery is achieved by the exit 
operator mechanism after the P-bit procedure has made the refer- 
enced area present. The processor has not yet fetched the first op- 
erator of the new procedure when this presence bit interrupt occurs; 
therefore, the PIR and PSR settings from the PCW or RCW , depending 
on whether an entry or exit was being performed, are saved when fab- 
ricating the RCW upon entry into the P-bit interrupt procedure. 



5-1^ 



Program Restart. In order to restart some operators after a pre- 
sence bit interrupt , it is necessary Tor the P-bit procedure to 
return either an IRW or D.D. The "RT-bit" in the presence bit I.D. 
(Pi) indicates to the P-bit procedure whether to perform an exit 
or return operator when returning to the interrupt program. The 
"RT-bit" is manipulated by the hardware prior to honoring the pre- 
sence bit interrupt. Figure 5-6 (Presence Bit Interrupt Table) 
illustrates the (PSR, PIR) , exit/return and "RT-bit" relationship 
to the various presence bit interrupt conditions. 

Segmented Array. 

This interrupt is used by the string operators as an upper limit 
boundary detection. Arrays in main memory may be segmented into 
groups of 256 words each, bounded on both ends by memory link words. 
Each word read from memory during string operator executions is 
checked for the presence of bit 48 (memory protect). If the bit is 
on, the segmented-array interrupt is set. String operator interrupts 
leave a special parameter in the A register. This indicates how 
many words in the stack, below the parameter, will be needed to 
restart the operation after the new segment of data has been brought 
to main memory. 



2 1 BIT 

o = ON 



OR OFF 



A Register Parameter 



24 



10 



M X 



Segmented Array Interrupt ID 



Programed Operator. 

This interrupt is used as detection for invalid operator codes. 
Primary codes BC , E7 > EF , F6 , and P7 are detected and cause the 
interrupt. Each family controller detects these codes. Any invalid 
code not detectable will result in a loop timer interrupt. The pro- 
gramed operator interrupts are used as communicate operators to 
the system. 

5-15 









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10 



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24 




O 








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O 



Programed Operator Interrupt ID 

Operator Independent Interrupts. 

These interrupts are induced by conditions outside the operator or 
processor logic. They are divided into two groups, External In- 
terrupts and Alarm Interrupts. 

External Interrupts . 

These interrupt conditions are anticipated and inform the system 
of some change in the external environment. They normally result 
in a momentary interruption of a program process which will be 
continued after handling or recording the interrupt condition. The 
external interrupts are recognized by the hardware operators. The 
program sequence controller senses the interrupt condition, inhibits 
activation of the next operator, and initiates an interrupt pseudo- 
operator in its place. PIR and PSR fields of the RCW address the 
next operator syllable so that the program will be restarted with 
the execution of the next syllable upon continuation. The external 
interrupts are: 

a. Processor to Processor interrupt 

b. Special Control interrupts 

1) Interval timer 

2) Stack overflow 

c. Multiplexor interrupts 

1) I/O finish 

2) Data Communications 

3) General Control Adapter 

k) Change of Peripheral Status 



5-17 



Processor to Processor. 

This interrupt is used to interrupt another Processor on the system. 
When a Processor executes a HEYU operator, an external interrupt is 
sent to all other system processors. When the interrupt is recog- 
nized by a Processor, its interrupt controller clears the A register 
and sets the B register equal to the ID. The normal Interrupt Pro- 
cedure entry is then executed. 



21 



EtIT 



X 



Processor to Processor Interrupt ID 

This interrupt is also used to initiate an Idle Processor on the 
system. It could also cause another Processor to suspend its op- 
eration on a program whose stack is about to be overlayed. 

Interval Timer. 

This interrupt is used for programmatic time slicing. The interval 
timer is activated by the SINT (Set Interval Timer) operator. The 
timer is set to the value of bits 10:11 of the B register and de- 
crements every 512 microseconds until equal to zero. At this time, 
if the timer is still armed, the interrupt is set, leaving the ID 
in the B register and A register cleared. The maximum interval is 
1 second. The timer is disarmed whenever the Processor handles an 
External interrupt. 



22 



x x 



BIT 



Interval Timer Interrupt ID 

Stack Overflow. 

This interrupt is used to inform the operating system that the Stack 
Controller has sensed the use of the highest address allotted for 
this program's stack (LOSR, limit of stack register). The program 
is halted to allow the Operating system the option of allocating a 



5-l< 



larger stack area or aborting the program. The interrupt controller 
leaves the A register cleared., the interrupt ID in the B register 
and PIR backed up if PROF is on. 

22 1 BIT 



X x 



Stack Overflow Interrupt ID 

Multiplexor Interrupts. 

The MPX interrupts may be handled by any system processor. A 
priority is established between multiplexors and processors to 
determine which Processor responds when an interrupt is present. 
This is necessary when multiple Processors and Multiplexors are 
present because they all share a common SCAN BUS. 

Scan Bus Control. 

Scan bus control is established by a closed loop circuit in which a 
control "bit" is passed from one Processor to another on every 3rd 
clock pulse. 

A Processor may initiate a scan-bus operation when it has the con- 
trol bit and the IIHF (inhibit external interrupt flip flop) is off. 

Priority Handling Example. 

Assume MPX-A and MPX-B have I/O finished interrupts occuring at the 
same time. Both Processors are operating with IIHF off and could 
therefore respond to an external interrupt. If both Processors were 
allowed to respond, a SCAN-IN of the interrupt literals would be 
attempted simultaneously on one common bus. 

The 2nd priority established, is a left to right (LTRP) , or right 
to left (RTLP) priority which allows a multiplexor to place its 
interrupt in the appropriate Processor. Figure 5-7 is a hypothetical 
system configuration that will be used for explanation. 



5-19 



Each of the Left- to-Right or Right- to-Left priorities are only true 
for one Processor at one time. LTRP is normally used to allow MPX-A 
to set its interrupt in Processor #1. RTLP is normally used to al- 
low MPX-B to set its interrupt in Processor #2. 

The priorities may be passed to another Processor when the IIHF is 
on. IIHF on in a Processor, causes the Priority to be passed and 
inhibits the interrupt controller from responding to any MPX in- 
terrupts. The priorities in a Processor are re-established when 
IIHF is reset. 

Priority Handling With IIHF Set. 

Assume Processor #1 had its IIHF set because it was in Control state. 
Setting this flip flop in Processor #1 causes the LTRP to be passed 
to #2. Now assume identical timed interrupts appear in both MPX-A 
and MPX-B. Both are recognized by the interrupt Controller in Pro- 
cessor #2. The interrupt controller in Processor #2 now assigned 
MPX-A the 1st priority and will subsequently SCAN-IN the interrupt 
literal from MPX-A while making MPX-B hold its interrupt line on. 
(The MPX interrupts are not reset until a SCAN- IN is performed.) 
The RTLP priority could also be passed to Processor #1 should it 
enter normal state while Processor #2 is in Control state, thus each 
system Processor is capable of handling external interrupts from 
either Multiplexor. 

I/O Finished Data Communications. 

Both interrupts are handled by the Interrupt Controller as follows: 

a. A SCNI (SCAN-IN) operator is forced into the Processor at 
the next SECL to read the interrupt literal into the B 
Register. 

b. An identification bit (20) is placed into the interrupt 
ID, the A register is cleared and PIR is backed up. 

c. The normal operation of entry to the Interrupt Handling 
Procedure is then executed. 



5-20 



20 7 6 5 4 1 BIT 

O = ON 



O 



OR OFF 



I/O Finished/Data Communications Interrupt ID 

NOTE 

Bits 1:2 identify which MPX 
the literal was read from. 
MPX-A=01, MPX-B=10. 

Bits 7:4 identify type of 
interrupt . 

1001=1/0 finished 

0001=DCP #1 

0010=DCP #2 

0011=DCP #3 

llll=Change of status 

General Control Adapter. 

This interrupt indicates a special control device such as an Analog- 
device, a plotter, or some machine being controlled by the system 
wished to communicate to the Processor. 

External MPX. 

This interrupt will be used when a second Multiplexor is connected 
to one of the k word- interfaces of a Multiplexor, and it wishes to 
have one of its interrupts recognized. 

Alarm Interrupts. 

These interrupt conditions are not anticipated and inform the system 
of some detrimental change in environment. They normally result from 
either a programing error or hardware failure. The alarm interrupt 
conditions are recognized upon occurrence by the interrupt control- 
ler. The interrupt controller seizes control of the machine, clears 
the activated operator family, marks the TOS registers full and ac- 
tivates the pseudo interrupt operator. In either case the current 
operator is terminated prematurely. The alarm interrupts are: 

5-21 



a. Loop 

b. Memory Parity 

c. MPX Parity 

d. Invalid Address 

e. Stack Underflow 

f . Invalid Program Word 

Loop. 

This interrupt is invoked if the Processor hardware fails to pro- 
vide a SECL (Syllable execute complete level) at least every 2 sec- 
onds. This could occur if an attempt is made to execute an invalid 
operator. Should the interrupt occur, the ID is left in the B reg- 
ister, the A register is cleared and PIR is backed up. 



25 



x x 



BIT 



Loop Interrupt ID 

Memory Parity. 

This interrupt is invoked if the Memory Controller detects an even 
number of bits being transmitted between the Processor and Memory. 
Should the interrupt occur, the ID is left in the B register, the A 
register is cleared and PIR is backed up. 





25 




1 






X 




X 





BIT 



Memory Parity Interrupt ID 

MPX Parity. 

This interrupt is the same as Memory Parity except it is used for 

Processor/Multiplexor transfer. 





25 




2 






X 




X 





BIT 



MPX Parity Interrupt ID 



5-22 




o 

in 
-P 

o 
o 

-p 

•H 
U 

o 

•H 
Oh 

PQ 

S 
aS 
o 
w 

o 
o 

pq 



i 

>A 

CD 
U 

•H 
fa 



«" a: L. 

« u O £ u < 



5-23 



Invalid Address. 

This interrupt is set by the Memory Controller upon detecting an 
attempt to access a non-existent Memory module by a failure to ob- 
tain an acknowledgement to a memory request within 8 clock periods. 
The Memory Controller initiates the. interrupt and the Interrupt Con- 
troller leaves the ID in the B register with the A register clear 
and PIR backed up. 



25 



BIT 





X 




X 





Invalid Address Interrupt ID 

Stack Underflow. 

This interrupt is invoked if the Stack Controller detects an attempt 
to move the S register to an address less than BOSR (Bottom of Stack 
Register) during stack adjustment. Should the interrupt occur, the 
ID will be left in the B register, the A register is cleared and 
PIR backed up. 



25 



BIT 





X 




X 





Stack Underflow Interrupt ID 

Invalid Program Word. 

This interrupt is invoked if one of the following conditions is en- 
countered : 

a. A word with a tag not equal to 3 is placed in the P reg- 
ister for execution. (Except in Table mode). 

b. The Variant operator is decoded as the second part of a 
2-syllable variant operator. 



5-2k 



c. The Processor is in EDIT mode and a family strobe is emit- 
ted for another operator family. Should the interrupt 
occur, the ID is left in the B register, the A register is 
cleared and PIR is backed up. 

25 5 bit 



1 



Invalid Program Word Interrupt ID 

Interrupt Handling. 

The occurrence of an interrupt condition causes the processor to 
enter an interrupt handling procedure after marking the stacks and 
inserting two interrupt parameters into the stack. The procedure 
entered is called from a reserved location (DO + 3) , relative to 
the base (trunk) of the MCP stack. Figure 5-8 depicts the stack 
format just prior to and after entering the interrupt procedure. 

The two interrupt parameters PI and P2 that are inserted into the 
stack as the interrupt condition is recognized are used to supply 
information describing the interrupt condition. The PI parameter 
identifies the interrupt type and instructs the interrupt procedure 
how to return to the interrupted program. The P2 parameter supplies 
supplementary information about the interrupt condition (e.g., in 
the case of some presence bit interrupts P2 is a copy of the non- 
present descriptor). 

The interrupt procedure is entered by inducing an enter operator 
with an IRW pointing to DO + 3 at F + 1 . The hardware expects to 
find a PCW at DO +3; however, an IRW or IRW chain pointing to a PCW 
are legitimate conditions. 

STRING OPERATOR CONTROLLER. The String Controller controls the char- 
acter handling operators. It is integrated with the F, G, and. H 
family hardware (figure 5-9) - This controller is unique in many 
ways. One of the ways is by having the E register initiate memory 
cycle requests via the memory controller, during logical stepping 

5-25 



OBJECT 
PROGRAM ^ 
STACK 



BOSR 



MCP 
STACK < 



DO 



P2 

~pT 



IRW 



DO +3 



MSCW 



OBJECT 

PROGRAM 

DATA 



TSCW 



SEG DESC, 



PCW 



RCW 



MSCW 











o 


JJEC 


T PROGRAM CODE 




















1 
























1 
















1 




. 


. 






c 



PBR 



PIR 



PSR 



INTERRUPT HANDLING PROCEDURE CODE 



□ 



STACK FORMAT PRIOR TO CALLING THE INTERRUPT PROCEDURE. 



OBJECT 
PROGRAM { 
STACK 



P2 



PI 



RCW 



MSCW 



TSCW 



INTERRUPTED OBJECT PROGRAM CODE 



MCP 
STACK 



DO 



MSCW 



PBR 
PIR 
PSR 



INTERRUPT HANDLING PROCEDURE CODE 



STACK FORMAT AFTER ENTERING THE INTERRUPT PROCEDURE 



Figure 5-8. Stack Format 



5-26 



of the operator flow. This allows simultaneous logic flow with mem- 
ory cycles, to accelerate the logic flow. The E register decoding 
is shown in figure 5-10 . 

The String OP Controller contains one OP code register for all 
three families. There are two sequence registers; the JF registers 
are used for the Family F sequence flow together with a sequence 
extension register KF . The JG registers are used for the Family G 
and H sequence flow together with a sequence extension register KG. 

CONTROL STATE/NORMAL STATE. Any B 6500 Processor has the ability to 
perform in either Normal or Control state. The difference between 
the two states is the inhibiting of external interrupts while per- 
forming in control state as well as enabling a few privileged opera- 
tors. The Normal Control State flip flop (NCSF) and Inhibit Inter- 
rupt flip flop (IIHF) are both set when operating in control state. 

The Processor switches to control state upon entering a procedure 
via a control state program control word or by the execution of 
disable external interrupt operator. Likewise it switches to normal 
state when entering a procedure via a normal state program control 
word or by the execution of the enable external interrupt operator. 

The Operators that are enabled in Control State are: 

a. Set Interval Timer 

b. Scan Out 



5-27 







STRING OP CONTROLLER 








OP8F 


OP4F 


OP2F 


OP1F 




OPCODE REG. 


8 


4 


2 


1 


E REG. 


FAMILY F 
















KF3 






JF3 


JF2 


JF1 


JFO 




KF2 










■ 




KF1 






FAMILY G, H 
















KG3 






JG3 


JG2 


JG1 


JGO J 


KG2 








KG1 















Figure 5~9 • String OP Controller 



E 
REG 



FUNCTION 



REG 



1 


READ 


Y 


2 


II 


B 


3 


" 


C 


4 


" 


X 


5 


" 


A 


9 


WRITE-PROTECT 


Y 


10 


" 


B 


11 


II 


C 


12 


II 


X 


13 


II 


A 


14 


OVER-WRITE 


X 


15 


II 


A 









Figure 5-10* E Register Functions 



5-21 



input/output multiplexor. 

The Input/Output Multiplexor and associated peripheral control 
modules are used to control data transfers between memory and all 
peripheral equipment, independent of the processor. The multi- 
plexor receives instructions from the processor and, together with 
its associated peripheral controls, executes them. Each multiplexor 
is capable of processing up to ten simultaneous i/O operations from 
up to 20 peripheral controls , handling a combined maximum of 2$6 
peripheral devices (figure 5-H)« 

SCAN BUS. 

The Scan Bus is the communications link between various components 
as seen in figure 5-11. It consists of 20 Address lines, 48 data 
Information lines, 1 Parity line and 11 Control lines. MPX or Data 
Communications operations are initiated via the Scan Bus. 

COMMAND DATA REGISTER. 

This 113 bit register is used with the Scratch Pad Memory for the 
control of Input Output data flow. The command portion of this reg- 
ister accepts an i/O Command from the Processor via the SCAN BUS 
and uses the data portion to accept or send information to the i/O 
devices via the peripheral control cabinets. Commands and partial 
data words are shuttled to and from the scratch pad memory between 
data character times. Full words are read or written to Main Mem- 
ory without Processor intervention. An expanded Command Data word 
is shown in figure 5-12. 

SCRATCH PAD MEMORY. 

The Scratch Pad contains 120 bits of IC memory per word. The i/O 
MPX may contain from h thru 10 such words. These words provide 
temporary storage locations between command data word character 
collection times. In this way one Command Data register can ser- 
vice up to 10 simultaneous i/O operations. A fixed assignment (l 
through 10 ) is given during the initiation of the i/O request and 
remains as such until the end of the i/O operation. The unit des- 
ignate field as seen in figure 5-12 reflects this assignment. 



5-29 











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5-30 



TAG REGISTER. 

The Tag Register (5 FF/SPM SLOT) associates a Scratch Pad Memory 
word with a specific i/O channel. This assignment is made when 
the initial i/O request is received from the Processor. 

MEMORY EXCHANGE. 

The Memory Exchange allows sharing of the Memory Interface lines 
between the MPX and Data Communications Processors. The Memory 
Exchange has 8 control lines , 20 address lines , 51 data lines and 
1 parity line to the Memory interface. 

INTERRUPT NETWORK. 

The MPX Interrupt Network informs the Processors of an interrupt 
condition in the MPX. This indication remains true until one of 
the Processors reads the interrupt by a SCAN-IN command. 

TIME OP DAY REGISTER. 

The Time of Day Register is comprised of 36 flip flops used to 

accumulate increments (2.4 pisec) of time. The system Processors 

set or read these registers via the SCAN BUS. 

CHANNEL ASSIGNMENT CONTROL. 

The Channel Assignment Control assigns a priority to specific i/O 
devices. This is a fixed physical assignment as per system re- 
quirements . 

CHARACTER TRANSLATOR. 

Data flow between the MPC and Peripheral devices is translated in 

one of three ways : 

a. Direct (no translation in the MPX) 

b. 6 bit INTERNAL to BCL or vice versa 

c. 8 bit EBCDIC to BCL or vice versa 



5-31 




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5-32 



PERIPHERAL CONTROL INTERFACE. 

The Peripheral Control Interface consists of 16 INFO lines and 12 
Control lines which are bussed to all of the Peripheral controls. 
Four additional control lines are sent to each Peripheral Control 
for a total of 80. The additional control lines are: 

a. BUSY/ - PCn 

b. ARL - PCn (Access Request Level) 

c. AGL - PCn (Access Granted Level) 

d. CDL - PCn (Channel Designate Level) 

The 16 info lines are used bi-directionally for 8-bit byte, or byte 
pair, transmission. 

DATA COMMUNICATIONS INTERFACE. 

The Data Comm Interface consists of 4, 20-wire cables sharing 2 
word interfaces. Busses 2 and h, 1 and 3 share the same memory 
request logic. Data Comm is routed through the MPX only to uti- 
lize the Memory Exchange of the Multiplexor. 

SYSTEM CLOCK CONTROL AND MDL PROCESSOR. 

The Multiplexor cabinet contains hardware that makes up the MDL 

Processor and System Clock. 

SYSTEM CLOCK. The system clock is generated by a 10 megahertz 
crystal oscillator and shaped into 25 and h5 nanosecond width 
pulses. A Central Control divides and controls the basic clock for 
distribution to the entire system as follows: 



a. Processor 



Type Basic Clock Arithmetic Clock 

B 5 megahertz 5 megahertz 

C 2.5 megahertz 2.5 megahertz 



5-33 



b. I/O Multiplexors 

5 megahertz 25 nanosec width 
I.67 megahertz 25 nanosec width 

c . Memory 

5 megahertz 25 nanosec width 

d. Peripheral Control 

I.67 megahertz 45 nanosec width 

e. Data Communications Processor 

5 megahertz 25 nanosec width 

MAINTENANCE DIAGNOSTIC PROCESSOR. The Maintenance Diagnostic Logic 
Processor (MDL) is a special purpose computer composed of an I/O 
Channel and a Data Processor. It is used for fault detection and 
isolation in the B 65OO Processor, B 65OO Multiplexors and the Per- 
ipheral Controls. The MDL Processor provides for three modes of 
operation: Display, Diagnose, and Detect. 

Display Mode. 

In this mode the MDL scan- out of eight flip flops per word pro- 
gresses continuously in a loop under control of the display logic. 
It is used for indication and control of Processor and MPX flip 
flops . 

Diagnose Mode. 

In this mode the MDL Processor reads test cases from a tape unit, 
thru an I/O Channel, to memory. The MDL uses this information for 
logical testing of system components and halts at the end of a 
string of test cases when a failure is diagnosed. 

Detect Mode. 



This mode of operation is initiated in the same manner as diagnose 
mode; however, the test procedure is halted after the first failure 
of a test case. 



5-3h 



INFORMATION FLOW FROM CARD READER TO MAIN MEMORY. 

The information flow between a Card Reader and main memory is 

shown in figure 5-13 • Three types cards may be read from the card 

reader. 

ALPHA CARD READ. 

Cards punched in the Alpha mode are decoded in the card reader 
from Card Code to 6-bit BCL EXTERNAL code. The character is 
transmitted to the information register in the Card Reader Control 
in the Peripheral Control Cabinet. The information (l character) 
is held until the Multiplexor honors an access request and places 
the appropriate SPM word in its Command/Data register. I/O des- 
criptor control bits k-2 (translate) and kl (6 or 8 bit) steer the 
character through the appropriate translator and place it in the 
next character position of the Data register. The data register 
can store 6 or 8 characters depending on the translator used. 
When the data register receives the last character of a word, a 
memory request cycle is initiated to write this full 52 bit word 
in memory. A tag field read is optional on this type of a card 
read, with any tag code (the first character of a word) allowable 
in this mode of operation. 

BINARY CARD READ. 

Cards punched in the binary mode contain twice as much information 
as those punched in Alpha mode. Each card column contains two char- 
acters. Positions 12, 11, 0, 1, 2 and 3 provide for one row of 
characters on the upper half while positions k, 5> 6, 7 > 8, and 9 
provide for another row of characters on the lower half. Control 
bits kZ and kl equal to zero bypasses the translator and causes 
direct transfer of information into the Data Register. The infor- 
mation contained in one card column is strobed twice (once for each 
half of the card) and presented to the multiplexor as two 6-bit 
characters. Tag read is optional in this mode but the only allow- 
able code is Program tag (3) • 



5-35 



EBCDIC CARD READ. 

Cards punched in the EBCDIC mode are read in a similar fashion 
as binary mode, upper and lower half. However, the actions within 
the Peripheral Control are quite different. Three translations are 
required within the control before an 8 bit EBCDIC code is present- 
ed to the MPX data register. The first two occur as the upper and 
then lower halves of the card are strobed into the information 
register. The information register at this point represents the 
12, 11, 0, 9 and 8 card punches directly and a binary configuration 
of punches 1 thru 7 as seen in figure 5-13. The information reg- 
ister is then decoded into EBCDIC code as it is presented to the 
information lines on its way to the Data register. When 6 bytes 
are collected in the data register, a memory request cycle is in- 
itiated to write the full 52 bit word. Tag read is optional in 
this mode with any tag code being permissable. 

NOTE 

Two other codes are available 
for use on the B 65OO system. 
They are ICT and BULL codes. 
Both are decoded by a special 
Alpha/Binary decoder (in the 
Card Reader) to BCL code. 

MEMORY AND MPX CONTROLLER. 

The Memory Controller responds to 21 commands decoded from nine 
INPUT lines. Figure 5-lk shows the k types of Memory Controller 
cycles that respond to these INPUT lines. During a core memory 
write, the contents of the cell being written are "flashed" back 
to the Processor. Certain Write operations are aborted by the 
memory if the memory protect bit (48) is on. 



5-36 




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MEMORY 
CONTROLLER 

RESPONDS TO 
21 COMMANDS 




l 


Z12 


2 


BUS 


3 


INPUT | 


4 


LINES 




5 




6 




7 




8 







MPRC TO MEMORY 



(PREVENTS MEMORY WRITE WHEN 
Z12-6 IS TRUE AND BIT (48) IS 
DETECTED IN WORD BEING 
WRITTEN INTO) 



TYPE OF 

REQUESTING 

OPERATOR 


MEMORY 

CONTROLLER 

FUNCTION 


MEMORY CONTROLLER 
Z 12 LEVELS 


PROCESSOR REGISTERS 
USED 


876543210 


READ 


READ ONLY 


o o o o o o 
o o o o o o 


A 
B 
C 
X 
Y 
P 



OVERWRITE, 
STACK ADJ., 
READ WITH 
LOCK 



OVERWRITE * 



1 


A 


1 


B 


1 


C 


1 


X 


1 


Y 



NOTE 

When the Overwrite function 
is used the Memory write is 
not aborted if the addressed 
area has the protect bit on. 

The Read With Lock operator 
exchanges the contents of the 
A register with the contents 
of memory addressed by the 
B register. 

Figure 5-l4. Memory Controller Decoding 



5-38 



PROTECTED 

WRITE 
(PSEUDO) 


PROTECTED* * 
WRITE 




1 
1 

1 

1 

1 


A 
B 
C 
X 
Y 



NOTE 

When this function is used 
Memory write is aborted by- 
detection of Protect bit. 
(no indication of abort 
is given) . 









1 


A 


STORE 
OPERATORS 


PROTECTED 
WRITE/READ 

* * * 




1 

1 
1 

1 


B 
C 
X 
Y 



Figure ^-lk. Memory Controller Decoding (cont) 
The Memory /MPX Controller contains the following sections: 

a. B 6500 Memory and MPX interface. 

b. Address Adder. 

c. Integrated Chip Memory. 

The interface consists of two sections: a memory bus and a scan 
bus . 

MEMORY BUS. The MEMORY BUS contains 20 address lines, 51 data (in- 
formation) lines, 1 parity line and 8 control lines. It transmits 
information bi-directionally between MEMORY and Processor "hard 
registers" A, B, C, X, Y and P. 

Control of the memory interface is thru the Z12 bus which is pro- 
duced by FUNCTIONAL CONTROLLERS and FAMILY OPERATOR CONTROLLERS 



5-39 



when a memory cycle is desired. 

SCAN BUS. The SCAN BUS contains 20 address lines, 48 data infor- 
mation lines, 1 parity line and 11 control lines. It provides 
an asynchronous communication path between the B 65OO Processors 
and B 65OO Multiplexors or B 65OO Data Communication Processors. 

ADDRESS ADDER. 

The Address Adder is a 20-bit parallel adder with inputs from the 
Z8 and Z9 busses, the Carry flip flop and the Subtract flip flop. 
The busses derive their addressing information from the 48 IC mem- 
ories or from the "hard registers" via the Z6 bus in the transfer 
controller. The Carry flip flop and Subtract flip flop are used 
to modify the output address. 

The output of the Address Adder is an input to the Memory Address 
register for memory selection or an input to one of the 20 bit IC 
memories . 

INTEGRATED CHIP MEMORY. 

The Memory Controller contains 48 IC memories, each containing 20 
bits. Thirty-two of these display the current address of an object 
program. These D registers (DO thru D31) provide for multiple le- 
vels of addressing. The D registers are controlled by Display 
READ/WRITE SELECT logic. 

The other 16 IC memories are divided into two groups, base and 
index (0 thru 7). Each is a 20-bit memory used by Family Operator 
logic and Program sequence flow for base and index addressing: 



a. 


PBR 


(0) 


b. 


SBR 


(1) 


c . 


DBR 


(2) 


d. 


TBR (BUF2) 


(3) 


e . 


S 


CO 


f . 


SNR 


(5) 


g. 


PDR 


(6) 


h. 


TEMP 


(7) 



PROGRAM BASE 

SOURCE BASE 

DESTINATION BASE 

TABLE BASE 

TOP OF STACK ADDRESS 

STACK NUMBER 

PROGRAM DICTIONARY INDEX 

TEMPORARY STORAGE 



5-40 



PROGRAM INDEX 
SOURCE INDEX 
DESTINATION INDEX 
TABLE INDEX 
LIMIT OF STACK 
BASE OF STACK 
POINTS TO TOP MSCW 
TEMPORARY STORAGE 



ORGANIZATION. 

Main memory in the B 6500 is organized so that any memory module 
can send information to, or receive information from both proces- 
sors and both I/O multiplexors over any one of four information 
busses (see figure 5-15). 



i . 


PIR 


(0) 


J • 


SIR 


(1) 


k. 


DIR 


(2) 


1. 


TIR (BUF3) 


(3) 


m. 


LOSR 


W 


n. 


BOSR 


(5) 


. 


F 


(6) 


P. 


BUF 


(7) 


MAIN MEMORY. 





170— 

MULTI- 
PLEXOR 
1 



PROCESSOR 
1 



MEMORY 

MODULE 

1 



<> 




MEMORY 

MODULE 

2 



-o 



<> 



MEMORY 

MODULE 

n 



-o 



-o 



o 



I 



Figure 5-15. Memory Organization 



5-^-1 



The modules examine each word that is placed on the bus to deter- 
mine whether that particular module is being addressed; if it is, 
linkage is set to receive the word. This eliminates the need for 
a central control to establish a linkage directing the word to the 
proper module. Two hundred nanoseconds after the memory cycle is 
initiated, the module grants access. In another 200 nanoseconds, 
the word is available to the bus, and 200 nanoseconds later the 
word is in the processor or I/O multiplexor register. Operation 
of each memory module is independent of the operation of any other 
memory module. Memory cycles can occur simultaneously within all 
four modules. 

Information is transmitted along the bus in parallel, as illustrated 
in figure 5-16. 

" 20 BIT ADDRESS 



6 BITS FOR 0-63 MODULES 
14 BITS FOR MEMORY ADDRESSES 0-16,383 



INFORMATION BUSS J 6 CONTROL BITS 



(READ, WRITE, BUSY, ETC.) 
52 INFORMATION BITS 



Figure 5- 16. Information Transmission 

MEMORY PROTECTION. 

Memory protection prevents one program from affecting another with 
a combination of hardware and software features. One of the hard- 
ware features is automatic detection of an attempt by a program 
to index beyond its assigned data area. Another is a memory pro- 
tect bit in each word to prevent user programs from writing into 
memory words which have the protect bit set. (The protect bit 
is set by the software.) Any attempt to alter protected data is 
inhibited and an interrupt is generated. Thus a user program 
cannot change program segments, data descriptors, or any program 
words or MCP tables during execution. 



5-42 



CABINET CONFIGURATION. 

The B 6500 Main Memory consists of 1 to 32 memory modules con- 
taining 16,384 words each. Up to three modules and associated hard- 
ware can be housed in one Memory Cabinet (49,152 words). Each cab- 
inet has a memory controller which responds to six requestors Tor 
memory accesses. The requestors are: 

a. Processor #1 or #2 

b. Multiplexors A or B 

c. Memory Testor 

d. MDL Processor 

INTERFACE . 

The requesting unit's memory interface contains five hubs (except 
for the MDL Processor). Each hub has 80 bus lines for bi-direction- 
al communication with memory. Each memory cabinet has six hubs, 
one hub for each possible requestor. A typical maximum size system 
is shown in figure 5-17. Notice how the hubs within the requestors 
are all tied to the same address and information flow lines. Take 
the example of a Processor requesting access to Memory module zero 
in cabinet zero. The Processor places the address and information 
on the busses. It is seen by all of the memory controls, but 
only accepted by module zero because of the address decoding in 
Memory Cabinet zero. This means that each Memory Control must have 
the ability to accept addresses from six different requestors and 
connect them to one of three memory modules. This is accomplished 
by a crosspoint control located within the memory control (figure 
5-18). There are three sets of crosspoint controls for each 
requestor within each memory control. Three requestors may gain 
simultaneous access to the same memory cabinet if they are addres- 
sing separate memory modules. 

PRIORITY. 

A priority system, which is activated prior to the crosspoint con- 
trols, prevents conflicts when more than one requestor is addres- 
sing the same memory module. 



5-43 




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5-44 



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L 

16384 
WORDS 




1 
















i 




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CONTROL 






MOD. 
M 

16384 
WORDS 




1 








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1 U 




CROSSPOINT 
CONTROL 




REQ 

#5 














CROSSPOINT 
CONTROL 




























— ■* 






















— *. 




MOD. 
N 

16384 
WORDS 




1 














1 










1 








REQ 




—*- 


#6 






















1 


ME 


MORY CABINET 






1 

.J 



Figure 5-18. Memory Module Selection 

Request hub #1 has the highest priority and any of the six request 
ing units can be attached to this point by the Field Engineer. 



5-^5 



MEMORY REGISTERS. 

Each Memory module contains 2 core stacks, a MIR ( a 52-bit memory 
information register), and the appropriate timing and control logic 
necessary for reading and writing (figure 5-19). The memory cycle 
is divided into two parts , a destructive read where the information 
is read into the MIR ' s , and a write into the cores from the MWR ' s . 
The MWR's are loaded from one of the six requesters. When a mem- 
ory protect bit (48) is on during the read portion of the cycle, 
and the operation is not overwrite, the information is rewritten 
from the MIR ' s . 



REQ 1 



REQ 2 



REQ 3 



REQ 5 



* REQ 6 






MWR 



STACK 



STACK 



MIR 



n 



i 
i 

1 MODULE I 

^ mmm ^ ■■• «■• «"^ «™» «m mmJ 



MEMORY 



Figure 5-19. Memory Registers 

MEMORY ADDRESSING. 

Memory modules are addressed by 20 bits (figure 5-20). Bits 
thru 13 are used for word selection and bits 14 thru 19 are used 
for module selection. 

MEMORY INTERLACING. 

Each memory module has the ability to interlace every other word 
to the next consecutive module. Interlacing is controlled by a 
pluggable jumper located on each module and provides the advantage 
of faster memory accesses when consecutive words are addressed. 



5-46 



Interlacing saves time because the next consecutive access may be 
requested in an adjacent module while the first module is finishing 
its cycle. Bit Ik of the module select address is exchanged with 
bit zero when interlacing is used. Examples of module and word 
selection when using the interlace option are shown in figure 5-20. 
This feature can be quickly enabled or disabled by a field engineer 



HEXADECIMAL 
ADDRESS 


INTERLACE 
ADDRESS 


MODULE 


WORD 


00000 


00000 








0000 1 


04000 


1 





04000 


00001 





1 


04001 


04001 


1 


1 


08000 


08000 


2 





08001 


OCOOO 


3 





ocooo 


08001 


2 


1 


ocooo 


OCOOO 


3 


1 


10000 


10000 


4 





10001 


14000 


5 










MODULE 
SELECT 




WORD 
SELECI 


r 


W/< 


15 


11 


7 


3 


18 


14 


10 


6 


2 


17 


13 


9 


5 


1 


16 


12 


8 


4 






Figure 5-20. Interlace Addressing 

MEMORY TESTING. 

Each system includes a test facility which can exercise any of the 

memory modules. When the test facility is being used with one of 

the memory modules, the other modules can be used by the system, 

if the module being tested is not interlaced. If it is, the option 

must be disabled before testing can take place. 

STACK CONTROLLER. 

The B 6500 provides automatic stack adjustment as required by the 
operators. These requirements are supplied to the Stack Controller 
on the Zll bus from the Operator Families and other Functional Con- 
trollers . 



The Stack Controller manipulates data between Main Memory and the 
A and B registers on both pop— up and push— down cycles. The X and Y 
registers are included in the adjustment cycles when double-preci- 
sion operands are involved. 

5-^7 



A typical program stack is shown in figure 5-21. The Stack Con- 
troller determines whether a pop-up or push-down cycle will be 
initiated. All other Controllers remain idle until an ADJC (Adjust 
complete) is sent to the Controller that initiated the adjustment. 




MSCW 



r^ 



i 



X REG 



Y REG 



BOSR 



TSCW 



> 



SOFTWARE 

ALLOCATED 

MEMORY 

AREA 



STACK CONTROLLER FUNCTIONS 




COMMAND 


OPERATION 


RESULT 


Zl 10 


EMPTY A AND B 


AROF 


BROF 








Zlll 


EMPTY A, FILL B 





1 


Zl 12 


EMPTY B, FILL A 


1 





Zl 13 


FILL BOTH 


1 


1 


Zl 14 


EMPTY A 





_ 


Zl 15 


FILL A 


1 


~ 


NOTE: 


= UNOCCUPIED 


1 = OCCUPIED 


- = STATUS WILL NOT BE USED BY 


THE OPERATOR CAUSING THE 


ADJUSTMENT 



Figure 5-21. Hardware Stack Adjustment 



5-48 



SECTION 6 
PROGRAM OPERATORS 



GENERAL . 



The machine language operators are composed of syllables in a 
program string. The operators are divided into three major classes , 
Primary, Variant and Edit.* The operators are either Primary Mode, 
Variant Mode, or Edit Mode. 

SYLLABLE ADDRESSING AND SYLLABLE IDENTIFICATION. 
SYLLABLE FORMAT AND ADDRESSING. 

A machine language program is a string of syllables which are nor- 
mally executed sequentially. Each word in memory contains six 
8-bit syllables. The first syllable of a program word is labeled 
syllable and is formed by bits k7 thru kO (figure 6-l). 



SYLLABLE 


SYLLABLE 


SYLLABLE 


SYLLABLE 


SYLLABLE 


SYLLABLE 





1 


2 


3 


4 


5 



47 


43 




39 


35 




31 


27 \ 






23 


19 




15 


11 




7 


3 


46 


42 


38 


34 


30 


26 | 


22 


18 


14 


10 


6 


2 


45 


41 


37 


33 


29 


25 


21 


17 


13 


9 


5 


1 


44 


40 


36 


32 


28 


24 


20 


16 


12 


8 


4 






Figure 6-1. Program Word 

P AND T REGISTERS. 

The P Register contains the currently active program word. The T 
Registers are the control (instruction) registers. There is one 
four-bit T register in each operator family. These registers con- 
tain the operation to be executed in a particular operator family. 
The four high-order bits of the operator syllable are decoded to 
select the operator family to receive the strobe pulse, (execute 
pulse). The PSR (Program Syllable Register) points to the next 
syllable to be used and also determines when a new program word is 
required in the P register. 



6-1 



When a new program word is required it is brought from the memory 
location indicated by the sum of PBR (Program Base Register) and 
PIR (Program Index Register). This program word is placed in the 
P register and PSR is set to the first syllable of the next op- 
erator. PIR is incremented by 1 to address the next required pro- 
gram word (figure 6-2). 



PROGRAM 
SEGMENT 



PROGRAM WORD 



PROGRAM WORD 



PROGRAM WORD 



PROGRAM WORD 



PROGRAM WORD 



PROGRAM INDEX REGISTER 



PROGRAM BASE REGISTER 



I 



"P" REGISTER 



1 



ADDRESS 
ADDER 



PSR 



OPERATOR FAMILY T REGISTERS 



OPERATOR FAMILY "T" REGISTERS 
Figure 6-2. Program Word, Syllable Addressing 

OPERATION TYPES. 

Operations are grouped into 3 classes: Name call, Value Call, and 
operators. The two high-order bits (bits 7 and 6) determine whether 
a syllable begins a Value Call, Name Call or operator (figure 6-3). 



6-2 



(bits 7 & 6) 


Syllable 


# of 


1 


Identification 


Type 


Syllables 


Function 


00 


Value Call 


2 


Brings an operand into 
the stack. 


01 


Name Call 


2 


Brings an IRW into the 
stack. 


IX 


Other Operators 


1 =) 12 


Performs the specified 
operation. 



Figure 6-3. Syllable Decode Table 

NAME CALL. Name Call builds an Indirect Reference Word in the 
stack. Stack adjustment takes place so that the "A" register is 
empty. The six low- order bits of the first syllable of this opera- 
tor are concatenated with the eight bits of the following syllable 
to form a l4-bit address couple. The address couple is placed, 
right- justified, into the "A" register, with the remainder of the 
"A" register set to zero. The TAG field of the "A" register is 
set to 001 and the register is marked full. 

VALUE CALL. Value Call loads into the top of the stack the operand 
referenced by the address couple formed in the same manner as in 
the Name Call operator. If the referenced Memory Location is an 
Indirect Reference Word or a Data Descriptor, additional memory 
accesses are made until the operand is located. The operand is 
then placed in the top of stack registers. The operand may be 
either single or double-precision, causing either one or two words 
to be loaded into the stack. 

OPERATORS. Operators vary from 1 to 12 syllables in length. The 
first syllable of each operator determines the number of additional 
syllables forming the operator. Upon completion of each operator, 
the program counter addresses the first syllable beyond all of the 
syllables comprising the operator. 



-3 



Operators work on data as either full words (48) data bits plus 
tag bits) or as strings of data characters. Word operators work 
with operands (single or double-precision) in the top of the stack 

String operators are used for transferring, comparing, scanning, 
and translating strings of digits, characters, or bytes. In ad- 
dition, a set of micro- operators provides a means of formating 
data for input/output. 

The string operators use source and destination pointers which are 
located in the stack. These pointers set the following hardware 
registers : 

a. Source Base Register - (SBR). 

b. Source Word Index Register - (SIR). 

c. Source Byte Index Register - (SIB). 

d. Source Size Register - (SSZ). 

e. Destination Base Register - (DBR) . 

f. Destination Word Index Register - (DIR) . 

g. Destination Byte Index Register - (DIB), 
h. Destination Size Register - (DSZ) . 

In some of the string operators the source pointer may not be used, 
In this case? an operand may be in the stack; its characters are 
circulated as it is being used. 

String operators have an optional Update function, producing up- 
dated source and destination pointers and count. At completion of 
an operation the source and destination pointers are updated as 
follows : 

a. If the source is an operand it is left in the stack. 

b. If the pointer is a descriptor, the Word Index fields and 
Byte Index fields are updated from SIR/DIR and SIB/DIB. 
The String Size fields are updated from SSZ/DSZ . 

c. If the pointer is a Data Descriptor or a non-indexed 
String Descriptor, it is converted to an Indexed String 
Descriptor and updated. 

6-h 



If both, the source and destination descriptors have size fields 
equal to zero, the size registers indicate 8-bit character size. 
When both a source and destination are required and the size field 
of one is equal to zero and the other is not, then the size field 
of the non-zero descriptor is used. 

If neither size field is equal to zero and the size fields are not 
equal and the operator is not Translate, the invalid operand inter- 
rupt is set and the operator is terminated. The size field is con- 
sidered equal to zero when the source is an operand. 

WORD DATA DESCRIPTOR. 

Word Data descriptors refer to data areas, including input/output 
buffer areas. The Word data descriptor defines an area of mem- 
ory starting at the base address contained in the descriptor. The 
size of the memory area in operands is contained in the length 
field of the descriptor. Word Data descriptors may directly refer- 
ence any memory word address from zero through 1,0485,575 (current 
maximum is 524,288 words). The structure of the Word Data descrip- 
tor is illustrated in figure 6-4 and contains the following: 





P. 
47 




R. 
43 








? : : : : : :;: ; ; : ; 


39 


35 


31 


27 


23 




19 


15 




11 


7 


3 


1 

50 


'•'.••.••••••'•.• : 


C. 
46 





42 




38 


LENC 
34 


JTH/II 
30 


MDEX 
26 


22 


M 
18 


EM/D 
14 


ISK A 
10 


DDRESS 
6 2 



49 




1. 
45 





41 






37 


33 


29 


25 


21 


17 


13 


9 


5 


1 


1 
48 


M&W$ 


S. 
44 


:'•:'■:':':'•:'• 


D. 
40 


: ; :-: : : : :!:-: 


36 

, 


32 


28 


24 


20 


16 


12 


8 


4 






Figure 6-4. Word Data Descriptor 

a. Bit 50:3, a tag of 101. 

b. Bit 47:1, the presence bit, indicates the presence or 
absence of data in main memory. A zero causes a presence 
bit interrupt whenever the descriptor is used by a pro- 
cessor to obtain non-present data. A one indicates that 
the data described is in main memory. 



6-5 



c. Bit 46:1, the copy bit. A zero indicates that this is the 
original descriptor for the particular data area. A one 
indicates that this descriptor is a copy of the original 
descriptor . 

d. Bit 45:1, the indexed bit. A zero indicates that an in- 
dexing- operation is required before the descriptor may be 
used to obtain data. A one indicates that indexing has 
already taken place and the index value is stored in bit 
positions 39:20 (Length/index). 

e. Bit 44:1, the segmented bit. A zero indicates that the 
data is not segmented. A one indicates that the data is 
divided into segments. 

f. Bit 43:1, the read-only bit. A zero indicates that the 
data may be referenced for reading or writing. A one in- 
dicates that the area cannot be used for data storage. 

g. Bit 42:2, a zero indicates a word data descriptor. 

h. Bit 40:1, the double-precision bit. A zero indicates sin- 
gle-precision operands, a one indicates double-precision 
operands . 

i. Bit 39:20, contains either the length of the memory area 
(if bit 45 = 0) or an index value (if bit 45 = l). If 
bit 45 equals zero, the descriptor has not been indexed. 
This field is used for size checking during the indexing 
operation. If bit 45 equals one, the descriptor has been 
indexed. For a double-precision operation, the index is 
doubled after index size checking, and the result is stored 
in the index field. 

j. Bit 19:20, contains either a main memory or disk address. 

If the presence bit (bit 47) equals one, this field contains 
the memory address of data. If the presence bit equals 
zero and the copy bit (bit 46) equals zero, this field 
contains the disk address of the data. If the presence 



6-6 



bit equals zero and the copy bit equals one, this field 
contains the memory address of the original descriptor. 

STRING DESCRIPTOR. 

String Descriptors refer to strings of 4-bit digits, 6-bit charaC' 
ters or 8-bit bytes. The String Descriptor defines an area of 
memory starting at the base address contained in the descriptor. 
The size of the memory area in characters is contained in the 
length field of the descriptor. The structure of the String Des- 
criptor is illustrated in figure 6-5 and contains the following 
information: 





P. 
47 






R. 
43 






39 


35 


31 


27 


23 




19 


15 


11 


7 


3 


1 

50 




C . pSl 






SZ. 

42 




LEN 
38 


GTH 
34 


NO 
30 


IARAC 
26 


TERS 
22 




MEM/DISK ADDRESS 
18 14 10 6 2 



49 




iiifi. 

• • : 45 




SZ. 

41 


37 


33 


29 


25 


21 




17 


13 


9 


5 


1 


1 
48 




S. 
44 




SZ. 
40 




36 


32 


28 


24 


20 




16 


12 


8 


4 






a 



b. 



Figure 6-5* String Descriptor (Non- indexed) 

Bit 50:3, a tag of 101. 

Bit 47:1 the presence bit. A zero causes a presence bit 
interrupt if the descriptor is used to access data. A 
one indicates the data is present in main memory. 

Bit 46:1, the copy bit. A zero indicates that this is 

the original descriptor for the particular data area. A 

one indicates that this descriptor is a copy of the ori- 
ginal descriptor. 

Bit 45:1, the indexed bit. A zero indicates indexing 
is required. A one indicates that indexing has taken 
place and the word and character index are length/index 
field (see figure 6-6). 



6-1 



e. Bit 44:1, the segmented bit. A zero indicates that the 
data area is not segmented. A one indicates that the data 
is segmented. 

f. Bit 43:1, the read only bit. A zero indicates that the 
data may be referenced for reading or writing. A one 
indicates that the data can be read only. 

g. Bit 42:3, character size field. 100 indicates 8-bit bytes, 
Oil indicates 6~bit characters, and 010 indicates 4-bit 
digits. 

h. Bit 39:20, contains either the length of the memory area 
(bit 45=0) or an index value (bit 45=l). When bit 45 
equals zero, this field contains the length of the area 
in digits, characters or bytes- This field is used for 
size checking during indexing operations . When bit 45 
is equal to one, bits 39:4 contain a. byte index and bits 
35*'16" contain a word index as illustrated in figure 6-6. 



B 

Y39 
-T — 
E 
38 

"l 

N37 
D — 

X36 






35 


31 


27 


23 


V 
34 


VORD 
30 


INDE 
26 


X 
22 


33 


29 


25 


21 


32 


28 


24 


20 



Figure 6-6. Byte/Vord Index Field 

i. Bit 19:20, contains either a main memory or a disk address. 
If the presence bit (bit 47) is one, the field contains a 
memory address of the data. If both the presence bit and 
the copy bit (bit 46) are equal to zero, the field contains 
the disk address of the non-present data. If the presence 
bit is zero and the copy bit is one, the field contains 
the memory address of the original descriptor. 



6-8 



SEGMENT DESCRIPTOR. 

The segment descriptor (figure 6-7) describes a program segment 

and contains the following information: 





P. 

47 










39 


35 


31 


27 


23 i 




19 


15 


11 


7 


3 



50 




C. 
46 




38 


LENGTH 
34 30 26 


22 ! 


MEM/DISK ADDRESS 
18 14 10 6 2 


1 

49 










37 


33 


29 


25 


21 i 


!7 


13 


9 


5 


1 


1 
48 


36 


32 


28 


24 


20 ! 


1 !6 


12 


8 


4 






Figure 6-7. Segment Descriptor 

a. Bit 50:3, a tag of Oil. 

b. Bit 47:1, the presence bit. A zero indicates that the 
segment is absent from main memory. 

c. Bit 46:1, the copy bit. A zero bit indicates that this 
is the original segment descriptor. A one indicates that 
this is a copy of the original segment descriptor. 

d. Bit 45:1, unused. 



e. Bit 44:5> unused. 



NOTE 



unused bits may be 
either zero or one. 

f. Bit 39:20, specifies the length of the program segment 
in words . 

g. Bit 19:20 contains either the main memory address or the 
disk file address. If the present bit (bit 47 equals one, 
the field contains the main memory address of the program 
segment. If both the presence bit and the copy bit (bit 46) 



6-9 



equal zero, the field contains the disk address of the 
non-present program segment. If the presence bit equals 
zero and the copy bit equals one, the field contains the 
absolute memory address of the original program segment 
descriptor. 

MARK STACK CONTROL WORD. 

The Mark Stack Control Word (MSCW) , with the Return Control Word, 
provides a linking mechanism for the history of previous control- 
register settings through the stack. 

The MSCW is placed in the stack by the Mark Stack operator. The 
MSCW is organized as illustrated in figure 6-8 and provides the 
following data: 





D.S. 
47 






43 


39 ||i 


.•i'ii'i 


35 


31 


27 


23 




V. 
19 


I: : : : : : : : : : : 


15 




11 


7 


3 



50 




E. 
46 


STAO 
42 


C NO. ill 
38 j!= 


Dl 
34 


SPLAC 
30 


EMEh 
26 


JT 
22 






LI 
18 


14 


10 


6 


2 


1 
49 




45 


41 


37 Hi 


33 


29 


25 


21 




17 




(DF) PREVIOUS " 
13 9 5 


1 


1 
48 


44 


40 


36 j!j 


32 


28 


24 


20 




■ ; 


16 


12 


8 


4 






Figure 6-8. Mark Stack Control Word 

a. Bit 50:3, a tag of Oil. 

b. Bit 47:1, the different- stack bit. A zero indicates that 
the stack-number field refers to the current stack. A 
one indicates that the stack-number field refers to a 
different stack. 

c. Bit 46:1, the environment bit. A zero indicates an in- 
active MSCW, generated directly by the Mark Stack operator. 
The procedure entry has not been performed. A one denotes 
an active MSCW generated upon entry into a procedure, at 
which time the environment fields (stack number, displace- 
ment, and value fields) are stored into the Mark Stack 
Control Word. 



6-10 



d. Bit 45:10, the stack-number field, contains the number of 
the stack from which the PCW was obtained at procedure- 
entry. 

e. Bit 35:16, the displacement field, which, when added to 
the stack base address, locates the Mark Stack Control 
Word of the prior lexicographic level. 

f. Bit 19:1, the value bit. A zero indicates that the MSCW 
was generated during any operation that will be restarted 
from the beginning. A one indicates that the operator 
must continue after the Exit or Return which refers to 
this MSCW (e.g., an accidental entry by a Value Call). 

g. Bit 18:5, the LL field denotes the lexicographical level 
at which the program was running when the procedure was 
entered. 

h. Bit 13:14, denotes the stack history. This field, locates 
in the stack, the preceding MSCW (i.e., the previous "F" 
register setting) . 

PROGRAM CONTROL WORD. 

The Program Control Word (PCW), and the Mark Stack Control Word 
are used during entry into a procedure. The organization of the 
PCW is illustrated in figure 6-9 and contains the following: 







47 


'••:••:•:•:•: 


43 


39 




35 




31 


27 


23 




N. 
19 




15 




11 


7 


3 


1 

50 


46 


42 


38 


P.S.R. 
34 


P 
30 


.I.R. 
26 


22 






L 
18 


L 
14 


10 


6 


2 


1 
49 






ST/ 

45 


41 


JO. 
37 


33 


29 


25 


21 




17 


;.■:'■:'■:■:■'•■ 


s 

13 


. D. 
9 


NDE> 
5 


1 


1 
48 


44 


40 


36 






32 


28 


24 


20 






16 


12 


8 


4 






Figure 6-9. Program Control Word 



6-11 



a. Bit 50:3, a tag of 111 



b. Bit 47 : 1 , unused, 



c. Bit 46:1, unused. 

d. Bit 45:10, stack number containing the PCW. 

e. Bit 350) defines the program syllable within the word 
located by PIR. 

f. Bit 32:13, an index to the Program Base Register. 

g. Bit 19:1, normal state (zero) or control state (one), 
h. Bit 18:5, the level of the procedure being entered. 



l . 



Bit 13:14, the segment descriptor index. Bits 12 through 
zero specify the value to be added to the address located 
by either D register zero or one. When bit 13 equals zero, 
D register zero is selected; when bit 13 equals one, D 
register one is selected. 



RETURN CONTROL WORD . 

The Return Control Word and the Mark Stack Control Word are used 
for subroutine handling. The Return Control Word stores the en- 
vironment to which the subroutine will return. The organization 
of the Return Control Word is illustrated in figure 6-10 and 
contains the following: 







E.S. 
47 






35 




31 


27 


23 




; N. 
1< 




15 




11 


7 


3 



50 


O. 
46 


IRS.R. 

i 34 


30 


P.I.R 
26 


22 




L 
18 


L 
I 14 


10 


6 


2 


1 
49 


T. 
45 


! 33 


29 


25 


21 


17 




13 


5.D. 

9| 


NDE> 
5 


( 

1 


1 
48 


F. 

44 




32 


28 


24 


20 


16 


12 


8 


4 






Figure 6-10. Return Control Word 



6-12 



a. Bit 50:3, a tag of Oil. 

b. Bit 47:1, External Sign flip flop. 

c. Bit 46:1, Overflow flip flop. 

d. Bit 45:1, True/False flip flop. 

e. Bit 44:1, Float flip flop. 

NOTE 

43:1 will probably be TFOF , 
True/False flip flop oc- 
cupied flip flop. 

f. Bit 43:8 unused. 

g. Bit 35:3, the program syllable of the operator to be ex- 
ecuted after return from the subroutine. 

h. Bit 32:13, the PIR setting of the operator to be ex- 
ecuted next in the calling routine. 

i. Bit 19:1, a normal state (zero) or control state (one) 
procedure . 

j. Bit 18:5, the level of the calling procedure when the RCW 
is generated (at procedure entry) . 

k. Bit 13:14, the segment descriptor index. Bits 12 through 
zero specify the value to be added to the address located 
by either D register or 1. When bit 13 = zero, D reg- 
ister zero is selected; when bit 13 = one, D register one 
is selected. 



6-13 



INDIRECT REFERENCE WORD. 

Referencing a variable within the current addressing- environment 
of a procedure is accomplished through the address couple in the 
Indirect Reference Word (iRW) , and the Segment Descriptor Index of 
the Program Control Word (PCW). Both references are relative to 
the D Register specified by the address couple. The bit format 
of the IRW is shown in figure 6-12. 

STUFFED INDIRECT REFERENCE WORD. 



Reference to variables outside the current environment is accom- 
plished by a (stuffed) SIRW. This addressing is relative to the base 
of the stack in which the variable is located. 

The SIRW contains the stack number, the location (DISP) of the 
MSCW, and the displacement of the variable relative to the MSCW. 
The absolute memory location of the variable is formed by adding 
the contents of DISP and displacement to the base address of the 
referenced stack from the stack descriptor. The contents of the 
SIRW (with the exception of displacement) is dynamic and is accu- 
mulated as the program is executed. The stack number and DISP 
fields are entered into the SIRW by a special operator (STFF). 
The bit format of SIRW is shown in figure 6-11. 







47 






43 


39 




35 


31 


27 


23 










11 


7 


3 



50 






1 

46 


42 


38 


D 
34 


ISPLA< 
30 


CEME 
26 


NT 
22 




INC 
10 


)EX Fl 
6 


ELD 
2 



49 






ST/ 

45 


41 


37 


33 


29 


25 


21 






9 


5 


1 


1 
48 


£::•:•:£ 




44 


40 


36 


32 


28 


24 


20 






12 


8 


4 






Figure 6-11. Stuffed Indirect Reference 



6-lh 







47 










11 


7 


3 



50 







46 




ADDRESS COUPLE 
10 6 2 



49 








13 


9 


5 


1 


1 
48 


12 


8 


4 






Figure 6-12. Normal Indirect Reference Word 

a. Bit 50:3, a tag of 001. 

b. Bit 47:1, unused. 

c. Bit 46:1, the environment bit. A one indicates a Stuffed 
IRW. A zero indicates a Normal IRW. 

d. Bits 45:10, stack number. When bit 46 equals one, speci- 
fies the number of the stack containing the address. 

e. Bit 45:26, unused, when bit 46 equals zero. 

f. Bit 35:16, displacement field. When bit 46 equals one, 
this value added to the stack base address locates a 
Mark Stack Control Word. 

g. Bit 19*6, unused. 

h. Bit 13J14, index field. When bit 46 equals one, the index 
value is added to the contents of the D register specified 
by the Mark Stack Control Word. Bit 13 is always zero. 

i. Bit 13:14, when bit 46 equals zero, is divided into two 
functional fields (figure 6-I3). Each field is variable 
in length. The first sub-field, designated LL, selects 
one of the D registers. The second sub-field is an index 
value which is added to the contents of the selected D 
register to form an absolute address. The lengths of the 
sub-fields are defined by the current program level as 
shown in Table 6-1. 



6-15 



Table 6-1 
Sub-Field Lengths 



Program 


Length of LL 


Length of Index 


Level 


Field (Bits) 


Field (Bits) 




0-1 


1 


13 


2-3 


2 


12 


4-7 


3 


11 


8-15 


« 

4 


10 


16-31 


5 


9 



PROGRAM LEVEL 
0-1 



PROGRAM LEVEL 
2-3 



PROGRAM LEVEL 
4-7 



PROGRAM LEVEL 
8-15 



PROGRAM LEVEL 
16-31 





INDEX 

FIELD 

12-0 


1 

13 









INDEX 

FIELD 

11-0 


1 
13 


2 
12 





4 
11 








INDEX 


1 
13 


FIELD 
10-0 


2 

12 









4 
11 

8 

10 


INDEX 


1 

13 
2 

12 




FIELD 
9-0 





4 
11 


INDEX 
FIELD 
8-0 




8 
10 


1 
13 


16 
9 


2 
12 







Figure 6-13. Program Level Bit Assignment 

NOTE 

The bit order of the 
LL field is inverted. 

STEP INDEX WORD. 

The Step Index Word figure 6-l4 is used by the Step and Branch op- 
erator, to increase efficiency in iteration loops. It contains 
the following information: 







47 


43 


39 




35 


31 


27 


23 








15 


11 


7 


3 


1 

50 


IN( 
46 


IREME 
42 


NT 
38 


F 
34 


INAL 
30 


VALU 
26 


E 
22 


CI 
14 


JRRENT VAL 
10 6 


.UE 
2 



49 


45 


41 


37 


33 


29 


25 


21 


13 


9 


5 


1 



48 


44 


40 


36 


32 


28 


24 


20 


12 


8 


4 






Figure 6-l4. Step Index Word 



6-16 



a 



Bit 50:3, a tag of 100. 



b. Bit 47:12, the value of the increment to be added to the 
current value field. 

c. Bit 35:16, the final value, used to terminate the iteration 
loop . 

d. Bit 19:4? unused. 

NOTE 
These bits must be zero. 

e. Bit 15:16, the current value or count. 



6-17 



SECTION 7 
PRIMARY MODE OPERATORS 



GENERAL. 



This section defines the primary operator's functions. In each, 
case the operator's name, mnemonic, and hexadecimal code is shown. 

The universal operators are also included in this section. 

ARITHMETIC OPERATORS . 

The arithmetic operators usually require two operands in the top 
of stack registers. These operands are combined by the arithmetic 
process specified with the result placed in the top of the stack. 
The operands may be either single-precision, double-precision, or 
intermixed. The specified arithmetic process adapts automatically 
to the data environment, with single-precision process invoked if 
both operands are of the single-precision type and a double-pre- 
cision process invoked if either operand is of the double preci- 
sion type. 

Each double-precision operand occupies two words. The second word 
of the operand is an extension of the first word of the operand, 
i.e., the mantissa of the first word of the operand may be an in- 
teger but the mantissa of the second word is always a fraction. 
When the top of stack registers are full, the first word of the 
first operand occupies the A register, the second word of the first 
operand occupies the X register. The first word of the second 
operand occupies the B register, the second word of the second op- 
erand occupies the Y register. Therefore, double-precision arith- 
metic processes operate on four words in the stack instead of two 
as in single-precision operations. Double-precision arithmetic 
leaves a two-word result in the top of the stack. 

Add, Subtract, and Multiply operations with two integer operands 
yield an integer result if no overflow occurs. If one or both 
operands is non- integer, or if the result generates an overflow, 
the result is non-integer. 



7-1 



Upon entry into any operator the hardware stack-adjust function 
fills or empties the top of stack register as required by the 
operator. If either register contains an incorrect word, the 
operator is terminated with an invalid operand interrupt. 

ADD (ADD) 80. 

The operands in the A register and the B register are added alge- 
braically with the sum left in the B register. At the end of the 
operation the A register is marked empty, and the B register is 
marked full. 

If only one of the operands is double-precision the single-preci- 
sion operand's extension register is set to zero. The B register 
is marked as a double-precision operand at completion of the op- 
eration. 

If the mantissa signs and the exponents are equal, the mantissas 
are added and the sum placed in the B register. If the sum exceeds 
13(26) octal digits, the mantissa of the sum is shifted right one 
octade, rounded, and the exponent is algebraically increased by 
one . 

If the exponents are equal but the mantissa signs are unequal, the 
difference of the mantissas with the appropriate sign is placed in 
the B register. 

If the exponents are unequal, the operands are first aligned. If 
the alignment causes the smaller operand to be shifted right 14(27) 
octal places, the larger operand is the result. 

If the alignment causes the smaller operand to be shifted right, 
but less than 14(27) octal places, the digits of the smaller oper- 
and shifted out of the register are saved and used to obtain the 
rounded result. 

If the signs of the operands are equal, the mantissas are added 
and the sum placed in the B register. If the sum does not exceed 
13(26) octal digits, the last digit shifted out of the register 

7-2 



is used to round the result. If the sum is 14(27) octades the 
mantissa in B (y) is rounded to 13(26) digits. 

If the signs of the operands are unequal, an internal subtraction 
takes place with the rounded result placed in the B register. 

If the result has an exponent greater than + 63 (+32,767), the ex- 
ponent overflow interrupt is set. If the result has an exponent 
less than -63 (-32,767) the exponent underflow interrupt is set. 

SUBTRACT (SUBT) 81. 

The operand in the A register is algebraically subtracted from the 
operand in the B register with the difference left in the B reg- 
ister. The operation is the same as for the Add operator except 
for initial sign comparisons. 

MULTIPLY (MULT) 82. 

The operand in the A register is algebraically multiplied by the 

operand in the B register. The rounded product is left in the B 

register. 

If the mantissa of either operand is zero, the B register is set 
to zero. 

If both mantissas are non-zero, the product of the mantissas is 
computed. If the product contains more than 13(26) digits, it i 
normalized and rounded to 13(26) digits. A mantissa of all seven 
is not rounded. 

If the result has an exponent greater than +63 (+32,767)? an ex- 
ponent overflow interrupt is set. If the result has an exponent 
less than -63 (-32,767), an exponent underflow interrupt is set. 

EXTENDED MULTIPLY (MULX) 8F . 

The operands in the A and B registers are algebraically multiplied 
and a double-precision product is placed in the B and Y registers. 
The A register is marked empty and the B register marked full. 



7-3 



s 
s 



The actions outlined for Multiply operations also apply to this 
operator. 

If either or both operands are double-precision, then a normal 
double-precision operation occurs. 

DIVIDE (DIVD) 83. 

The operand in the B register is algebraically divided by the 
operand in the A register, with the quotient left in the B regis- 
ter. After the operation the A register is marked empty, and the 
B register is marked full. 

If the mantissa of the B register is zero, the B register is set 

to zero. If the A register mantissa is equal to zero, the divide 

by zero interrupt is set. In either case the operation is termi- 
nated . 

If the mantissas of both operands are non-zero, they are normalized 
and the operand in the B register is divided by the operand in the 
A register. The quotient is developed to 14(27) digits, rounded 
to 13(26) digits, and left in the B register. 

If the result has an exponent greater than +63 (32,767) the exponent 
overflow interrupt is set. If the result has an exponent less than 
-63 (32,767) the exponent underflow interrupt is set. 

INTEGER DIVIDE (iDIV) 84. 

The operand in the B register is algebraically divided by the op- 
erand in the A register and the integer part of the quotient is 
left in the B register. After the operation the A register is 
marked empty and the B register is marked full. 

If the mantissa of the B register is zero, the B register is set 
to zero. If the mantissa of the A register is zero, the divide by 
zero interrupt is set. The operation is terminated, in either case. 

If the mantissas of both operands are non-zero, they are normalized. 
If the exponent of the B register is algebraically less than the 



1-h 



exponent of the A register after both operands have been normalized, 
the B register is set to zero. If the exponent of the B register 
is algebraically equal to or greater than the exponent of the A 
register the divide operation proceeds until an integer quotient 
or a quotient of 13(26) significant digits is calculated. 

If an integer quotient is developed, the quotient is left in the 
B register with zero exponent for S.P. and the exponent set to 13 
for D.P. If a non- integer quotient is developed, the integer 
overflow interrupt is set. 

REMAINDER DIVIDE (RDIV) 85. 

The operand in the B register is algebraically divided by the op- 
erand in the A register to develop an integer quotient. The re- 
mainder of this Division is left in the B register. If this re- 
mainder is an integral value it is in the form of an integer (ex- 
ponent = for S.P., 13 for D.P.). After the operation the A 
register is marked empty, the B register is marked full. 

If the mantissa of the B register is zero, the B register is set 
to zero. If the mantissa of the A register is zero the divide by 
zero interrupt is set. In either case the operation is terminated. 

If both mantissas are non-zero, both operands are normalized. If 
the exponent of the B register is algebraically less than the ex- 
ponent of the A register after both operands have been normalized, 
the operand in the B register is the result. If the exponent of 
the B register is algebraically equal to or greater than the ex- 
ponent in the A register, the divide operation proceeds until an 
integer quotient is developed and the remainder is then placed in 
the B register. 

If a non- integer quotient is developed, the integer overflow in- 
terrupt is set and the operation is terminated. 

INTEGERIZE, TRUNCATED (NTIA) 86. 

The operand in the B register is converted to integer form without 

rounding and left in the B register. 

7-5 



If the operand in the B register can not be integerized, i.e., the 
exponent is greater than the number of leading zeros in the oper- 
and, the integer overflow interrupt is set and the operation is 
terminated . 

INTEGERIZE, ROUNDED (NTGR) 87. 

The operand in the B register is converted to integer form. Round- 
ing takes place if the absolute value of the fraction is greater 
than k. The rounded result is left in the B register. 

If the operand in the B register can not be integerized, i.e., the 
exponent is greater than the number of leading zeros in the oper- 
and, the integer overflow interrupt is set and the operation is 
terminated. 

The operand is rounded if necessary by adding one to the mantissa. 
If a non- integer results from this operation, the integer overflow 
interrupt is set. 

TYPE-TRANSEER OPERATORS . 

SET TO SINGLE -PRECIS I ON, TRUNCATED (SNGT) CC . 

The operand in the B register is set to a single-precision operand, 

or in the case of a data descriptor, the double-precision bit is 

set to zero. 

If the word in the B register is a non- indexed, double-precision 
data descriptor, the double-precision bit is cleared to zero and 
the length field multiplied by 2. 

If the double-precision operand in the B register has an exponent 

greater than + 63 the exponent overflow interrupt is set. If the 

exponent is less than -63 exponent underflow is set, and the op- 
eration is terminated. 

If the operand in the B register is a double-precision operand 

with an exponent less than +63 or greater than -63 the operand is 

normalized, and the tag field in the B register is set to single 
precision. 



7-6 



If the word in the B register is not an operand or a Data Descrip- 
tor, then the invalid operand interrupt is set and the operation 
terminated. 

If the operand is single-precision, it is normalized and the opera- 
tion is terminated. 

SET TO SINGLE- PRECISION, ROUNDED (SNGL) CD. 

The operand in the B register is changed to a rounded, single- 
precision operand. 

If the double-precision operand in the B register has an exponent 
greater than + 63 the exponent overflow is set. If the exponent is 
less than -63 the exponent underflow is set. In either case the 
operation is terminated. 

If the operand in the B register is a double-precision operand with 
an exponent less than +63 or greater than -63 the operand is nor- 
malized, the tag field in the B register is set to single-precision, 
and the operand in the B register is rounded from the Y register. 
The Y register is set to zero. 

If a carry is developed during the rounding operation the operand is 
adjusted and the new exponent is checked as above. 

If the operand is a single-precision operand, the operand is nor- 
malized and no rounding occurs. The action is as stated for the 
Set to Single-Precision, Truncated. 

SET TO DOUBLE- PRECISION (XTND) CE . 

The word in the B register is set to a double-precision operand with 
the Y register set to zero. If a single-precision data descriptor 
is present in the B register the double precision bit is set to one. 

If the word in the B register is a data descriptor with both the 
index bit and double-precision bit zero, the double-precision bit 
is set to one and the length field is divided by two. 



7-7 



If the operand in the B register is a double-precision operand 
the operation is complete. If it is a single-precision operand 
the tag field in the B register is set to double-precision and the 
Y register is set to all zeros. 

If the word in the B register is not an operand or a Data Descrip- 
tor, then the invalid operand interrupt is set and the operation 
terminated. 

LOGICAL OPERATORS . 
LOGICAL AND (LAND) 90. 

Each bit of the B operand, except for the tag bits, is set to one 
where a one appears in the corresponding bit positions in both the 
A operand and the B operand. The other information bits of the B 
operand are set to zero. The tag of the B operand is not disturbed, 
unless the tag of the A operand specifies double-precision, in which 
case, the B operand tag is set to double-precision. 

LOGICAL OR (LOR) 91. 

All bit positions of the B operand except the tag bits, are set to 
one if the corresponding bit position in either the A operand or 
the B operand is one, otherwise the bit is set to zero. The tag 
bits are set to the value of the second item in the stack except 
when the A operand is double-precision, in which case, the B reg- 
ister tag is set to double-precision. 

LOGICAL NEGATE (LNOT) 92. 

Every bit in the A operand is complemented except the tag field, 

which remains unchanged. 

LOGICAL EQUIVALENCE (LEQV) 93. 

Each bit of the B operand is set to 1 except the tag bits, when 
the corresponding bits of the A operand and the B operand are equal. 
Each bit of the B operand is set to except the tag bits, when the 
corresponding bits of the A and B operands are not equal. The tag 
field is normally set to the value of the second item in the stack 
except when the A operand is double-precision, in which case the 
B register tag is set to double-precision. 

7-8 



RELATIONAL OPERATORS . 

The relational operators perform algebraic comparison on the op- 
erands in the A register and the B register. The single precision 
result is left in the B register. The result is an operand in in- 
teger form with the value one if the relationship has been met or 
an operand with all information bits set to zero if the relation- 
ship was not met. All relational operations compare the B operand to 
the A operand. 

LOGICAL EQUAL (SAME) 9k. 

All bits, including tag bits, of the A operand and B operand are 
compared. If all bits are equal, a single precision operand with 
bit zero set to one and all other information bits set to zero is 
stored in the B register. Otherwise, a single-precision operand 
with all information bits set to zero is stored in the B register. 

GREATER THAN (GRTR) 8A. 

If the B operand is algebraically greater than the A operand, the 
B register is set to an integer form one. Otherwise, all bits in 
the B register are zero. 

GREATER THAN OR EQUAL (GREQ) 89. 

If the B operand is algebraically greater than or equal to the A 
operand, the B register is set to an integer form one. Otherwise, 
all bits in the B register are zero. 

EQUAL (EQUL) 8C. 

If the operands in the B and A registers are algebraically equal, 
the B register is set to an integer form one. Otherwise, all bits 
in the B register are zero. 

LESS THAN OR EQUAL (LSEQ) 8B . 

If the B operand is algebraically less than or equal to the operand 
in the A register, the B register is set to an integer form one. 
Otherwise, the B register bits are all zero. 



7-9 



LESS THAN (LESS) 88. 

If the operand in the B register is algebraically less than the 
operand in the A register, set the B register to an integer form 
one. Otherwise, the bits in the B register are all zero. 

NOT EQUAL (NEGL) 8D. 

If the operand in the B register is not algebraically equal to the 
operand in the A register, set the B register to an integer form 
one. Otherwise, the bits in the B register are all cleared to 
zero . 

BRANCH OPERATORS . 

Branch instructions break the normal sequence of serial instruction 
fetches. Branching may be either relative to the base address of 
the current program segment or to a location in another program 
segment. Branch operators may be conditional or unconditional. 

BRANCH FALSE (BRFL) AO . 

If the low order bit of the A register is zero, the Program Index 
Register and Program Syllable Register are set from the next two 
syllables in the program string. Otherwise, PIR and PSR are ad- 
vanced three syllable positions. 

The two syllables following the actual operator syllable form the 
new PIR and PSR settings as follows: The three high order bits are 
placed into Program Syllable Register and the next 13 low order 
bits are placed in the Program Index Register. The Program Regis- 
ter (P) is marked empty to cause an access to the new program word. 

BRANCH TRUE (BRTR) Al . 

If the low order bit of the A register is one, the Program Index 
Register and Program Syllable Register are set from the next two 
syllables in the program string. Otherwise, PIR and PSR are ad- 
vanced three syllable positions. The Branch True Operator uses 
the two syllables as described for the Branch False operator. 

BRANCH UNCONDITIONAL (BRUN) A2 . 

Program Index Register and the Program Syllable Register are set 

7-10 



from the next two syllables of the program string. The Branch 
Unconditional operator uses the two syllables as described for the 
Branch False operator. 

DYNAMIC BRANCH FALSE (DBFL) A8. 

If the low order bit of the B register is zero and the word in the 
A register is a Program Control Word, or an indirect reference to 
one, branch to the specified syllable of that program segment. 

If the low order bit of the B register is zero and the word in the 
A register is an operand, PIR and PSR are set from this operand. 

If the word in the A register is an operand, it is used in the 
following manner: The operand is made into an integer. If it is 
negative or is greater than 16,384, the invalid index interrupt is 
set and the operation is terminated. If bit zero of the operand 
is zero, PSR is set to zero, otherwise PSR is set to three. The 
next higher order 20 bits are placed in the Program Index Register. 
The Program Register is then marked empty to cause access to the 
new program word. 

DYNAMIC BRANCH TRUE (DBTR) A9 . 

If the low order bit of the B register is one and the word in the A 
register is a Program Control Word, or an indirect reference to one, 
branch to the specified syllable of the program segment. 

If the low order bit of the B register is one and the word in the A 
register is an operand, PIR and PSR are set from this operand. 

The operand in the A register is used in this operator in the man- 
ner described for the Dynamic Branch False operator. 

DYNAMIC BRANCH UNCONDITIONAL (DBUN) AA. 

If the word in the A register is a Program Control Word or an in- 
direct reference to one, branch to the specified syllable of the 
program segment. 

If the word in the A register is an operand, PIR and PSR are set 
from this operand. 

7-11 



The operand in the A register is used in this operator in the same 
manner described for the Dynamic Branch False operator. 

STEP AND BRANCH (STBR) A4. 

The increment field of the step- index word addressed by the contents 
of the A register, is added to its current-value field. If the 
current-value field is then greater than the final- value field, 
Program Index Register and Program Syllable Register are set from 
the next two syllables from the program string. Otherwise, Program 
Index Register and the Program Syllable Register are advanced three 
syllables. The step- index word is replaced in memory. 

If no SI¥ is in memory, and if an operand, is found, it is 
left in the stack. The A register is set to zero, PIR/PSR are ad- 
vanced and the next operator is executed. If no operand is en- 
countered, the invalid operand interrupt is set. 

UNIVERSAL OPERATORS . 

NO OPERATION (NOOP) FE. 

No operation takes place when this syllable is encountered. PIR 

and PSR are advanced to the next operator. This operator is also 

valid in Variant Mode and Edit Mode. 

CONDITIONAL HALT (HALT) DF. 

This operator halts the processor if the conditional halt switch 
is in the ON position. If the conditional halt switch is OFF, the 
operator is treated as a NOOP. This operator is also valid in 
Variant Mode and Edit Mode. 

INVALID OPERATOR (NVLD) FF. 

This operator sets the invalid operand interrupt. It is also valid 

in Variant Mode and Edit Mode. 

STORE OPERATORS . 

The store operators use the words in the A register and B register. 
The operand in the B register is stored in memory at the location 
addressed by an Indirect Reference Word or a Data Descriptor. If 
the A register contains an operand a hardware interchange takes 

7-12 



place so that the operand is in the B register. 

STORE DESTRUCTIVE (STOD) B8. 

If the word in the A register is an operand the A and B operands are 
interchanged. The Data Descriptor or IRW in the A register is the 
address in memory where the operand in the B register (B, Y regis- 
ters) is stored. After the operand is stored, the A register and 
the B register are marked empty and the operation is complete. 

If the word addressed by the Indirect Reference Vord is a Program 
Control Word, accidental entry occurs. 

If the word addressed by the Data Descriptor has the memory protect 
bit on (bit k8) , the memory protect interrupt is set and the opera- 
tion is terminated. 

If the presence bit in the Data Descriptor is zero the presence bit 
interrupt is set. After the data has been made present the opera- 
tion is restarted. 

STORE NON- DESTRUCTIVE (STON) B9 • 

This operator functions the same way as the Store Destructive opera- 
tor except that at the completion of this operator the operand is 
left in the B register. 

OVERWRITE DESTRUCTIVE (OVRD) BA . 

This operator functions the same way as the Store Destructive, 

except that it overrides memory protection checks. 

OVERWRITE NON- DESTRUCTIVE (OVRN) BB . 

This operator functions the same way as the Store Non-Destructive, 

except that it overrides memory protection checks. 

STACK OPERATORS . 

EXCHANGE (EXCH) B6. 

The operands in the A register and the B register are exchanged. 

The A and B registers may contain either operands or control words. 

The control words are treated as operands by this operator. 



7-13 



DELETE TOP OF STACK (DLET) B5 . 

This operator marks the A register empty. 

DUPLICATE TOP OF STACK (DUPL) B7 . 

The operand found in the B register is copied into the A register. 

The A register is marked full. 

PUSH DOWN STACK REGISTERS (PUSH) B4. 

This operator stores the valid word/words from the A register and/ 
or B register into the memory portion of the stack. The A and B 
registers are marked empty. 

LITERAL CALL OPERATORS . 

LIT CALL ZERO (ZERO) BO. 

This operator sets the A register to zero and marks the register 

full. The result is a single-precision operand. 

LIT CALL ONE (ONE) Bl . 

This operator sets the A register low order bit (bit 0) to one, 
leaving all other bits set to zero. The A register is marked full, 
The result is a single-precision operand. 

LIT CALL 8 BITS (LT8) B2. 

The syllable following the operator is the literal value to be 
placed in the A register bits 7:8. The rest of the A register is 
set to zero. The A register is marked as full and the Program 
Syllable Register is set to the syllable following the literal. 

LIT CALL 16 BITS (LT16) B3 . 

The next two syllables following the operator are a l6-bit literal 
value that is placed in the A register bits 15:16. The rest of 
the register is set to zero. The A register is marked full and 
PSR is advanced past the 16-bit literal. 

LIT CALL 48 BITS (LT48) BE. 

The next program word is placed in the A register, and the A reg- 
ister tag is set to zero. The A register is marked full, and PIR 
and PSR are advanced to the program syllable following the 48-bit 
literal value. This operator requires that the 48 bit literal in 
7-14 



the program string be word synchronized if the operator syllable is 
in any syllable position other than syllable 5> "the syllables in- 
tervening are not executed and are filled with invalid OP-Codes . 

MAKE PROGRAM CONTROL WORD (MPCW) BF . 

This operator performs a Lit Call 48 Bits as described above; how- 
ever, the tag is set to a PCW (ill) and the Stack Number Register 
is placed in bits 45:10. The A register is marked full. 

INDEX AND LOAD OPERATORS . 
INDEX (INDX) A6. 

The Index operator places the integerized value of the B register 
into the 20-bit length/index field of the Descriptor in the A reg- 
ister. The Descriptor is marked indexed (bit 45 is set to one). 
The A register is marked full and the B register is marked empty. 

If the word in the A register is an operand, the A operand is ex- 
changed with the B operand. If the word in the A register is 
neither a Descriptor nor an Indirect Reference Word Pointing to a 
Descriptor, the invalid operand interrupt is set and the operation 
is terminated. 

If the indexing value is negative or greater than or equal to the 
length field of the Descriptor the invalid index interrupt is set 
and the operation is terminated. 

If the descriptor is segmented, the index is partitioned into two 
portions by dividing it by the proper divisor determined by the 
type of data referenced by the descriptor, (d. p. word-128, s. p. 
word-256, 4-bit digit-3072, 6-bit character-2048, or 8-bit byte- 
1536). The quotient is used as an index to the given descriptor to 
fetch the array-row descriptor. The remainder is used to index 
the row descriptor. 

If the Double-Precision bit (bit 45) in the Descriptor is one, 
the index value in the B register is doubled. The balance of the 
operation is as described in the first paragraph of this operator. 



7-15 



INDEX AND LOAD NAME (NXLN) A5 . 

This operator performs an Index operation, then after the word in 
the A register is indexed, the Data Descriptor pointed to by this 
word is brought to the A register. The Copy bit (bit 46) of the 
Data Descriptor is set to one and the A register is marked full. 
If the presence bit (bit 47) is off, the address of the original 
descriptor is placed in ihe address field of the stack copy. If 
the word accessed by the index word in the A register is not a Data 
Descriptor the invalid operand interrupt is set and the operation 
is terminated. 

If the Data Descriptor accessed by the indexed word in the A reg- 
ister has the Index bit (bit 45) set to one the invalid operand 
interrupt is set and the operation is terminated. 

INDEX AND LOAD VALUE (NXLV) AD. 

This operator performs an Index operation, then after the word in 
the A register is indexed the operand pointed to by this descriptor 
is brought to the A register. The A register is marked full. 

If the word accessed is other than an operand the invalid operand 
interrupt is set and the operator is terminated. 

LOAD (LOAD) BD. 

The Load operator places the word addressed by the IRW or INDEXED 

DATA DESCRIPTOR in the A register. 

If at the start of this operator the A register contains other than 

a Data Descriptor or an Indirect Reference Word pointing at a Data 

Descriptor, the invalid operand interrupt is set and the operation 
is terminated. 

If the word pointed at by the Data Descriptor is another Data Des- 
criptor, that Data Descriptor is marked as a copy (Copy bit [bit 46] 
is set to one) and if the presence bit (bit 47) is off, the address 
of the original is placed in bits 19:20 of the copy in the stack. 



7-16 



SCALE OPERATORS. 

Higher-level languages such as COBOL require integer arithmetic. 
The Scale Operators provide the means of aligning decimal points 
prior to performing the arithmetic operations. In addition, the 
Scale Right operators provide for binary to decimal conversions. 

SCALE LEFT (SCLF) CO. 

This operator uses the second syllable as the scale factor. The 
operand to be scaled is placed in the B register and integerized. 
The resulting integer is then multiplied by 10 raised to the power 
specified by the scale factor. 

If scaling of a single-precision operand results in overflow the 
single-precision operand is converted to a double-precision inte- 
ger. A double-precision integer is defined as a double-precision 
operand with an exponent equal to 13 • 

If scaling of the operand results in an exponent greater than 13 > 
(double-precision operand) , the overflow FF is set to one. 

DYNAMIC SCALE LEFT (DSLF) CI. 

This operator performs the same operation as the Scale Left opera- 
tor; however, scale factor is taken from the A register rather than 
the program syllable following the operation syllable. The op- 
erand in the A register is integerized before the scale. 

SCALE RIGHT SAVE (SCRS) Ck . 

This operator uses its second syllable as the scale factor. The 
operand to be scaled is placed in the B register and is then in- 
tegerized. The resultant integer is then effectively divided by 
10 raised to the power specified by the scale factor. 

The quotient resulting from the division is left in the A register. 
The operand in the B register is the remainder which is converted 
to decimal (h bit digits) and is left justified. A and B registers 
are both marked full. 

If the scale factor is greater than 12, the invalid operand inter- 
rupt is set and the operation is terminated. 



7-17 



DYNAMIC SCALE RIGHT SAVE (DSRS) C5. 

This operator performs the same operation as the Scale Right Save 
operator; however, the scale factor is obtained from the A regis- 
ter rather than the program syllable following the operation syl- 
lable. The operand in the A register is integerized before being 
used. 

SCALE RIGHT TRUNCATE (SCRT) C2. 

This operator performs a Scale Right function using its second syl- 
lable as the scale factor. The B register is marked as empty at 
the conclusion of this operator. 

DYNAMIC SCALE RIGHT TRUNCATE (DSRT) C3. 

This operator performs the same operation as the Scale Right Trun- 
cate except that the scale factor is found in the A register and 
is first integerized by the operator. 

SCALE RIGHT FINAL (SCRF) C6. 

This operator performs a Scale Right operation except that the 
quotient in the A register is deleted by marking the A register 
empty. The sign of the quotient is placed in the external sign 
flip flop. 

If the quotient was non-zero at the conclusion of the operation the 
overflow flip flop is set. 

DYNAMIC SCALE RIGHT FINAL (DSRF) C7 . 

This operator performs a Scale Right Final operation with the scale 
factor found in the A register which is integerized by the opera- 
tor before use. 

SCALE RIGHT ROUNDED (SCRR) C8. 

This operator performs a Scale Right operation and the quotient is 
rounded by adding one to it if the most significant digit of the 
remainder is equal to or greater than five. The remainder is de- 
leted from the stack by marking the B register empty. 



7-18 



DYNAMIC SCALE RIGHT ROUND (DSRR) C9- 

This operator performs a Scale Right Rounded operation with the 

scale factor found in the A register. 

BIT OPERATORS . 

The Bit operators are concerned with a specified bit in the A reg- 
ister and/or B register. 

BIT SET (BSET) 96, 

This operator sets a bit in the A register. The bit that is set 
is specified by the program syllable following the operation 
syllable . 

If the program syllable defining the bit to be set has a value 
greater than 47, the invalid- operand interrupt is set and the op- 
eration is terminated. 

DYNAMIC BIT SET (DBST) 97- 

This operator performs a Bit Set Operation upon the bit specified 
by the operand in the top of stack register. This word is integer- 
ized before using it as a bit number. 

If the word in the top of stack register is not an operand an in- 
valid operand interrupt is set and the operation is terminated. 

If after being integerized the operand is less than zero or greater 
than 47, an invalid operand interrupt is set and the operation is 
terminated . 

BIT RESET (BRST) 9E. 

This operator resets a bit in the A register. The bit that is reset 

is specified by the syllable following the operation syllable. 

If the program syllable defining the bit to be reset has a value 
greater than 47, an invalid- operand interrupt is set and the opera- 
tion is terminated. 



7-1! 



DYNAMIC BIT RESET (DBRS) 9F. 

This operator performs a Bit Reset operation upon- the bit specified 

by the operand in the top of stack register. 

If the word in the top of the stack register is not an operand an 
invalid operand interrupt is set and the operation is terminated. 

If after being integerized the operand is less than zero or greater 
than 47, an invalid operand interrupt is set and the operation is 
terminated. 

CHANGE SIGN BIT (CHSN) 8E. 

The sign bit (bit 46) of the top-of-stack operand is complemented, 

i.e., if it is a one it is set to zero, if zero it; is set to one. 



TRANSFER OPERATORS. 

The Transfer Operators transfer any field of bits from one word in 

the stack to any field of another word in the stack. 

FIELD TRANSFER (FLTR) 98. 

This operator uses its following three syllables to establish the 
pointers used in the field transfer. This is done in the following 
manner: The second syllable of the operator is K. The third syl- 
lable of the operator is G. The fourth syllable of the operator 
sets the L register. 

The field in the A register, starting at the bit position addressed 
by G is transferred into the B register starting at the bit position 
addressed by K. The length of the field in the A and B registers 
is defined by L. When the specified number of bits have been trans- 
ferred, the A register is set to empty the B register is marked full 
and the operation is complete. 

If the second or third syllables of the operator are found to be 
greater than 4 7 or the fourth syllable is greater than 48, the in- 
valid operand interrupt is set and the operation is terminated. 



7-20 



DYNAMIC FIELD TRANSFER (DFTR) 99. 

This operator performs a Field Transfer operation with the exception 
that the B register operand is L. The B register is then reloaded 
from the stack and this operand is G. The B register is again 
loaded from the stack and this operand is K. 

If any of the three operands is a non- integer, it is first integer- 
ized. Each is checked for a value less than zero or greater than 
47 or 48 as specified in Field Transfer above. If either of these 
conditions exist in any one of the three operands, an invalid op- 
erand interrupt is set and the operation is terminated. 

FIELD ISOLATE (iSOL) 9A. 

This operator isolates a field of the word in the A register placing 
it right justified in the B register. The balance of the B regis- 
ter is cleared to zeros. The A register is marked empty and the B 
register is marked full. 

The operator uses its second and third syllables as the BIT pointers 
The second syllable of the operator addresses the starting bit of 
the field in the A register. The third syllable of the operator 
specifies the length of the field to be isolated. 

If the value of the second syllable is greater than 47 or the value 
of the third syllable is greater than 48 an invalid operand inter- 
rupt is set and the operation is terminated. 

DYNAMIC FIELD ISOLATE (DISO) 9B . 

This operator performs a Field Isolate operation except that the 
first item in the stack specifies the length of the field to be 
isolated. The second operand in the stack addresses the bit in the 
word of the third item in the stack that is to be isolated. 

If after being integerized the value of the first item in the stack 
is less than zero or greater than 47 an invalid operand interrupt 
is set and the operation is terminated. 



7-21 



If after being integerized the value of the second item in the 
stack is less than zero or greater than 48 an invalid interrupt is 
set and the operation is terminated. 

FIELD INSERT (iNSR) 9C . 

This operator inserts a field from the A register into the B regis- 
ter word. The field in the A register is right justified with the 
length of the field specified by the third syllable of the operator. 
The second syllable of the operand addresses the starting bit of the 
field in the B register. At completion the A register is marked 
empty and the B register is marked full. 

If the value of the second syllable of the operator is greater 
than 47 an invalid operand interrupt is set and the operation is 
terminated. 

If the value of the third syllable of the operator is greater than 
48 an invalid operand interrupt is set and the operation is ter- 
minated. 

DYNAMIC FIELD INSERT (DINS) 9D. 

This operator performs a Field Insert operation except the first 
item in the stack is used as the insert field data. The second 
item in the stack is used to specify the length of the field. The 
third item in the stack is used to address the starting bit in the 
receiving field in the B register. "When operation is complete the 
A register is marked empty and the B register is marked full. 

If after being integerized the value of the second item in the 
stack is less than zero or greater than 48 an invalid operand inter- 
rupt is set and the operation is terminated. 

If after being integerized the value of the third item in the stack 
is less than zero or greater than 47 an invalid operand interrupt 
is set and the operation is terminated. 



7-22 



STRING TRANSFER OPERATORS . 

String Transfer operators give the system the ability to transfer 
characters or words from one location in memory to another location 
in memory. The source and destination pointers are set from String 
Descriptors in the stack. 

TRANSFER WORDS, DESTRUCTIVE (TWSD) D3. 

This operator requires three items in the top of the stack, an op- 
erand, a String Descriptor or operand, and a String Descriptor. 
The first operand is integerized and used as the count or repeat 
field. The second item is either the source data or a descriptor 
which points at the source string and the third item is used to 
address the destination string. The number of words specified by 
the repeat field are transferred from the source to the destina- 
tion. At completion of the operation the A and the B registers 
are marked empty. 

This operation calls the Execute Single Micro, Transfer Words , and 
End Edit operators before continuing with the program string. 

If the memory protect bit is found on during the execution of the 
Transfer Words operator, the segmented array interrupt is set and 
the operation is terminated. 

TRANSFER WORDS, UPDATE (TWSU) DB. 

This operator performs the Transfer Words operator except that at 
the completion of the transfer of data, the source and destination 
pointers are updated to point to the location in memory where the 
transfer ended. The A and B registers are both marked full. 

TRANSFER WORDS, OVERWRITE DESTRUCTIVE (TWOD) D4. 

This operator performs a Transfer Words, Destructive operation, 

overriding the memory protection checks. 

TRANSFER WORDS, OVERWRITE UPDATE (TWOU) DC. 

This operator performs a Transfer Words, Update operation, over- 
riding the memory protection checks. 



7-23 



TRANSFER WHILE GREATER, DESTRUCTIVE (TGTD) E2 . 

This operator transfers characters from a location in memory point- 
ed to by the source pointer, to a location in memory pointed to by 
the destination pointer, until the number of characters specified 
has been transferred or the compare fails. 

The first item in the stack is used as the delimiter. The second 
item in the stack is the maximum number of characters to be trans- 
ferred. The third item in the stack is the source data or a source 
pointer and the fourth item in the stack is the destination pointer. 

The delimiter character is retained while a call Execute Single 
Micro operator initiates this operation. The character count is 
placed in the repeat field register as the EXSD is completed. The 
source and destination strings are checked for memory protection. 
The source character is then compared with the delimiter. The 
result of the compare is set in the True/False flip flop. If the 
condition is met the TFFP is set to one, if it is not met it is 
set to zero. 

If the number of characters transferred was equal to the repeat 
field the True/False flip flop will remain set to one. The A 
and B registers are marked empty and the operation is complete. 

If the comparison fails, the number of characters not transferred 
is placed in the A register and the True/False flip flop is set to 
zero . 

If the first operand in the stack is not a S.P. operand an invalid 
operator interrupt is set and the operation is terminated. 

If either the source or destination word has a memory protect bit 
on (bit 48=1) the segmented array interrupt is set and the opera- 
tion is terminated. 

If the second item in the stack is a descriptor it is used as the 
source pointer and the length field or repeat field is set to 1,048, 
575. All comparisons are binary (EBCDIC Collating Sequence). 

TRANSFER WHILE GREATER UPDATE (TGTU) EA . 
7-24 



This operator performs a Transfer While Greater operation and up- 
dates the source pointer and destination pointer to point at the 
next characters in the source and destination strings. The Repeat 
count is updated to give the number of characters not transferred. 
If the operation is terminated because the relationship is not met, 
the source pointer points at the character that failed the com- 
parison. 

TRANSFER WHILE GREATER OR EQUAL, DESTRUCTIVE (TGED) El. 

This operator performs a Transfer While operation using the relation 

greater than or equal to. 

TRANSFER WHILE GREATER OR EQUAL, UPDATE (TGEW) E9 . 

This operator performs a Transfer While Greater or Equal operation. 
The source pointer, destination pointers, and count are updated 
at the conclusion of the operator. 

TRANSFER WHILE EQUAL, DESTRUCTIVE (TEGD) E4. 

This operator performs a Transfer While operation with the relation 

used in comparison being equal. 

TRANSFER WHILE EQUAL, UPDATE (TEGU) EC. 

This operator performs a Transfer While Equal operation. The source 
pointer, the destination pointer and count are updated at the con- 
clusion of the operator. 

TRANSFER WHILE LESS OR EQUAL, DESTRUCTIVE (TLED) E3- 

This operator performs a Transfer While operation, using the Less 

than or Equal comparison. 

TRANSFER WHILE LESS OR EQUAL, UPDATE (TLEU) EB. 

This operator performs a Transfer While Less or Equal operation. 
The source pointer, destination pointer and count are updated at 
the conclusion of the operator. 

TRANSFER WHILE LESS, DESTRUCTIVE (TLSD) EO . 

This operator performs a Transfer While operation using the Less 

than c ompar i s on . 



7-25 



TRANSFER WHILE LESS, UPDATE (TLSU) E8. 

This operator performs a Transfer While Less operation. The source 
pointer, destination pointer and count are updated at the conclusion 
of the operator. 

TRANSFER WHILE NOT EQUAL, DESTRUCTIVE (TNED) E5 . 

This operator performs a Transfer While operation, with the not 

equal comparison. 

TRANSFER WHILE NOT EQUAL, UPDATE (TNEU) ED. 

This operator performs a Transfer While Not Equal operation. The 
source pointer, the destination pointer and count are updated at 
the conclusion of the operator. 

TRANSFER UNCONDITIONAL, DESTRUCTIVE (TUND) E6. 

This operator performs a Transfer While Greater or Equal, Destruc- 
tive operation forcing a zero delimiter. This causes all charac- 
ters to be equal or greater than the delimiter thus transfer will 
continue for the length of the repeat field. 

TRANSFER UNCONDITIONAL, UPDATE (TUNU) EE. 

This operator performs a Transfer Unconditional operation. The 
source pointer, the destination pointer and count are updated at 
the conclusion of the operator. 

STRING ISOLATE (SISO) D5 . 

This operator places in the top of the stack, right justified, the 
number of characters specified by the repeat field. The first item 
in the stack is the number of characters in the repeat field. The 
second item in the stack is either an operand or a descriptor used 
as the source pointer. 

This operator calls and executes the Execute Single Micro, Single 
Pointer operation before proceeding as above. 

If the number of bits to be transferred is greater than 48 the item 
is double-precision. 

If the number of bits is greater than 96 an invalid operand inter- 
rupt is set and the operation is terminated. 

7-26 



If the source data has the memory protect bit (bit 48) set to one 
the segmented array interrupt is set and the operation is terminated. 

COMPARE OPERATORS . 

The Compare Operators perform the specified compare of two strings 
of data. The True/False flip flop is conditioned by the results 
of the compare. 

COMPARE CHARACTERS GREATER, DESTRUCTIVE (CGTD) F2. 

This operator compares the characters of the two character strings. 
If the characters in the B string are greater than the characters 
in the A string the True/False flip flop is set to one. If not 
the True/False flip flop is set to zero. 

The first item in the stack is an operand which contains the length 
of the fields being compared. The second item in the stack is an 
operand or a descriptor pointing at the character string to be 
compared against. The third item in the stack is a descriptor 
pointing at the character string to be compared. 

The operator compares characters until it encounters a pair which 
are unequal. If the B string character is greater than the A string 
character, the TRUE/FALSE F.F.is left set otherwise it is reset. 
Memory access then continues until the repeat count is exhausted. 

If the Repeat count is less than or equal to zero, the True/False 
F.F. is reset. 

If either of the data strings has the memory protect bit on (bit 
48=1 ) the segmented array interrupt is set and the operation is 
terminated . 

All comparisons are by the binary character position in the col- 
lating sequence. 

COMPARE CHARACTERS GREATER, UPDATE (CGTU) FA. 

This operator performs a Compare Characters Greater operation. The 
source pointer and destination pointer are updated at the conclusion 
of the operator. 

7-27 



COMPARE CHARACTERS GREATER OR EQUAL, DESTRUCTIVE (CGED) Fl . 
This operator performs the Compare Characters operation with the 
comparison being greater than or equal. If the repeat count < 0, 
the True/False flip flop is set to zero. 

COMPARE CHARACTERS GREATER OR EQUAL, UPDATE (CGEU) F9. 
This operator performs a Compare Character Greater or Equal opera- 
tion. The source pointer and destination pointer are updated at 
the conclusion of the operator. 

COMPARE CHARACTERS EQUAL, DESTRUCTIVE (CEGD) F4. 

This operator performs the Compare Characters operation using the 

Equal comparison. If the repeat count < 0, then TFFF is set to one 

COMPARE CHARACTERS EQUAL, UPDATE (CEGU) FC . 

This operator performs a Compare Characters Equal operation. Th e 
source pointer and destination pointer are updated at the conclu- 
sion of the operator. 

COMPARE CHARACTERS LESS OR EQUAL, DESTRUCTIVE (CLED) F3 . 
This operator performs the Compare Characters operation with the 
Less than or Equal comparison. If the repeat count < 0, then TFFF 
is set to zero. 

COMPARE CHARACTERS LESS OR EQUAL, UPDATE (CLEU) FB. 
This operator performs a Compare Characters Less or Equal opera- 
tion. The source pointer and destination pointers are updated at 
the conclusion of the operator. 

COMPARE CHARACTERS LESS, DESTRUCTIVE (CLSD) FO. 

This operator performs the Compare Characters operation with the 
Less than comparison. If the repeat count < 0, the TFFF is set 
to zero. 

COMPARE CHARACTERS LESS, UPDATE (CLSU) F8. 

This operator performs a Compare Characters Less operation. The 
source pointer and the destination pointer are updated at the con- 
clusion of the operator. 



7-28 



COMPARE CHARACTERS NOT EQUAL, DESTRUCTIVE (CNED) F5 . 
Hhis operator performs the Compare Characters operation using the 
Not equal relation. If the repeat count < 0, then TFFF is set to 
zero . 

COMPARE CHARACTERS NOT EQUAL, UPDATE (CNEU) FD. 

This operator performs a Compare Characters Not Equal operation. 
The source pointer and the destination pointer are updated at the 
conclusion of the operator. 

EDIT OPERATORS . 

TABLE ENTER EDIT, DESTRUCTIVE (TEED) DO. 

This operator is used to control edit micro-instructions. These 
edit micro-instructions are contained in memory as a table and not 
as part of the normal prog-ram string. Upon entering this operator 
program execution is transferred to a table of micro- instructions . 
The last micro-instruction in this table must be the End Edit op- 
erator (see section 9)« The table contains Edit Mode operators. 

The first item in the stack is a descriptor pointing to the table 
of Edit Micro-Instructions. The second item in the stack is a S.P. 
operand or a descriptor pointing at the source string. The third 
item in the stack is a descriptor pointing at the destination. 

If the first item in the stack is not a descriptor the invalid 
operand interrupt is set and the operation is terminated. 

If the second item in the stack is a S.P. operand it is the source 
string. 

If the third item in the stack is not a descriptor the invalid op- 
erand interrupt is set and the operation is terminated. 

If the destination pointer descriptor has the Read Only bit set to 
one (bit 43) the memory protect interrupt is set and the operation 
is terminated. 



7-29 



If the length is less than 13 the operand in the top of the stack 
is a single-precision operand. If the operand is 13 or greater 
the result is a double-precision operand. 

If the length is not less than 25 an invalid operand interrupt is 
set and the operation terminated. 

If the second item in the stack is an operand it is the source 
string, and is composed of 8-bit bytes. 

If the source data has the memory protect bit (bit 48) set to one 
the segmented array interrupt is set and the operation is terminated 

PACK, UPDATE (PACU) D9. 

This operator performs a Pack operation, updating the source pointer 

at the completion of the operator. 

INPUT CONVERT OPERATORS . 

INPUT CONVERT, DESTRUCTIVE (iCVD) CA . 

This operator converts either 6-bit BCL code, 8-bit EBCDIC or 4-bit 

digit code to an operand for internal arithmetic operations. 

The first item in the stack is an operand that is integerized to 
form the repeat field. The second item in the stack is a descrip- 
tor used as a source pointer. 

The Input Convert operator calls on the Pack operator. After this 
operation is complete the 4-bit digit operand is converted to an 
operand of the equivalent binary value. 

The sign of the converted operand is then set from the True/False 
flip flop. If the converted operand is a single-precision operand 
the True/False flip flop is then set to one. If the converted 
operand is a double-precision operand the True/False flip flop is 
set to zero . 



7-31 



At the completion of the operator the B register is marked full. 
The tag field is set to indicate either a single or a double-pre- 
cision operand. 

If the item in the top of stack after being integerized is greater 
than 23 the invalid operand interrupt is set and the operation is 
terminated . 

INPUT CONVERT, UPDATE (iCVU) CB . 

This operator performs an Input Convert operation. The source 

pointer is updated at the completion of the operator. 

READ TRUE FALSE FLIP FLOP (RTFF) DE . 

This operator places the status of the True/False flip flop into 
the low order bit position of the A register. The rest of the A 
register is set to all zeros. The A register is marked full at 
completion of this operator. 

SET EXTERNAL SIGN (SXSN) D6. 

This operator places the mantissa sign of the top word of the stack 
in the External Sign flip flop. This operand is not deleted from 
the stack at the end of the operation,, 

READ AND CLEAR OVERFLOW FLIP FLOP (ROFF) D7 . 

Places the status of the Overflow flip flop in the least significant 
bit of the A register, sets the rest of the A register to zero, 
marks the register full and sets the Overflow flip flop to zero. 

SUBROUTINE OPERATORS . 
VALUE CALL (VALC) 00 => 3F . 

This operator loads into the A register the operand addressed by 
the address couple formed by the concatenation of the six low order 
bits of the first syllable and the eight bits of the following syl- 
lable. The A register is marked full. Figures 7-1 and 7-2 are 
simplified flow charts of the Value Call operator. 

This operator makes multiple memory accesses if the word accessed 
is either an indexed descriptor, Program Control Word, or an In- 
direct Reference Word. 

7-32 



If the word accessed is an indexed Data Descriptor the word ad- 
dressed by the Data Descriptor is brought to the top of the stack. 
If the double-precision bit (bit 40) in the Data Descriptor is 
equal to one, the other half of the double-precision operand is 
brought to the X register. 

If the word accessed by the Data Descriptor is another indexed Data 
Descriptor the word addressed by that Data Descriptor is brought to 
the top of the stack, and the above paragraph is repeated. 

If a Data Descriptor does not address an operand SIW or another in- 
dexed Data Descriptor an invalid operand interrupt is set and the 
operation is terminated. 

If the word accessed by the Value Call is an Indirect Reference 
Word the word addressed by the IRW is accessed and evaluated. If 
the word is an operand it is placed in the top of the stack. 

If the word accessed by the Indirect Reference Word is another IRW 
the operation continues as described above. 

If the word accessed by the Indirect Reference Word is an indexed 
Data Descriptor the operator proceeds as described above for Data 
Descriptors . 

If the word accessed by the Indirect Reference Word is a Program 
Control Word an accidental entry into the subroutine addressed by 
the PCW is initiated. A Mark Stack Control Word and a Return 
Control Word are placed in the stack and an entry into the program 
is made. Upon completion of the program a Return operator will 
re-enter the flow Value Call at the label IRW, figure 7-2. . 

NAME CALL (NAMC) kO => 7F . 

This operator builds an Indirect Reference Word in the A register. 
The address couple is formed by concatenating the 6 low order bits 
of the first syllable and the 8 bits of the following syllable. 
The A register is marked full and the operation is complete. 



7-33 




REMEMBER 

ALL 

VALUE 

CALL 

DATA 




DESC 




YES 



ADJ. 
(0,2) 



IRW 



OPERANDS- 



PLACE 

OPERAND 

IN 

"A" REGISTER 




NORMAL 




YES 



OBTAIN OTHER 

HALF OF OPERAND 

IN 

"X" REGISTER 



OP. 
COMPLETE 



OBTAIN 

WORD ADDRESSED 

BY IRW 




YES 



YES 



"ACCIDENTAL 

ENTRY" 
(CALL ON A 
PROCEDURE) 



YES 




NO 



DESC. 
FIG 
7-2 



Figure 7-1. Flow of Value Call Operator 



7-3^ 



DESC. 




NO 





YES 



NO 




YES 




OBTAIN 

WORD 

ADDRESSED 

BY DESC. 



NO 




NO 



YES 



OBTAIN 

STACK VECTOR 

DESC. 




NO 




YES 



OBTAIN WORD 

ADDRESSED 

BY DESC. 




NO 



OBTAIN WORD 

ADDRESSED 

BY 

SIRW 




YES 



NO 



INVALID 

OPERAND 

INTERRUPT, 




Figure 7-2. Flow of Value Call Operator (cont) 



7-35 



EXIT OPERATOR (EXIT) A3. 

This operator returns to a calling pi-ocedure from a called proce- 
dure resetting all control registers from the Return Control Word 
and the Mark Stack Control Word. The Exit operator does not re- 
turn a value to the calling routine. Figure 7-3 shows a simpli- 
fied flow chart of the Exit operator. 

RETURN OPERATOR (RETN) A7 . 

This operator performs an Exit operator with the exception that 

an operand or name in the B register is returned to the calling 

procedure. If a name is returned, and the V bit (bit 19 ) in the 

MSCW is on, the name is evaluated to yield an operand as described 

in VALC. Figure 1 -h shows a simplified flow chart of the Return 

operator. 

ENTER OPERATOR (ENTR) AB . 

This operator is used to cause an entry into a procedure from a 
calling procedure. Entry is to the program segment and syllable 
addressed by the Program Control Word. Figure 7-5 shows a simpli- 
fied flowchart of the Enter operator. 

The Enter operator accesses the Indirect Reference Word at F + 1 
which points to the Program Control Word. The operator then builds 
a Return Control Word into the stack at F + 1. 

EVALUATE (EVAL) AC. 

This operator loads the A register with an indexed Data Descriptor 
or an Indirect Reference Word that addresses A "target", which 
may be an SIW, an Un- Indexed Data Desc, a String Desc , or an op- 
erand. The "target" may be referenced through a chain of descrip- 
tors, accidental entries, or Indirect Reference Words. In any 
case memory accesses will continue to be made until the target is 
located. The A register is left containing the Data Descriptor or 
the Indirect Reference Word which addresses the target. Figure 7-6 
is a simplified flow chart of the Evaluate operator. 



7-36 







ADJ (0, 0) 



OBTAIN 

RCW 
AT (F+ 1) 



SET UP 

REGISTERS TO RETURN 

TO PRIOR PROCEDURE, 

SAVE BOSR AND CUT 

BACK THE STACK 




YES 




NO 



OBTAIN WORD 

ADDRESSED 

BY(F) 




NO 



YES 



COMPUTE 

ADDRESS OF 

PREVIOUS 

MSCW 





CHECKIT 




OBTAIN PREVIOUS 

MSCW AND 

SAVE ADDRESS 




YES 




YES OBTAIN NEW 
J STACK AND 
SAVE 
ADDRESS INFO. 



NO 




UPDATE D[^] 

AND 
OBTAIN NEW 

MSCW 



NO 



OBTAIN SEG. DESC. 

ADDRESSED BY PDR. 

SET PBRTO ADDRESS 

IN S.D.&CAUSE A FETCH 




OPER. 
COMPLETE 



Figure 7-3 • Flow of Exit Operator 



7-37 



(return) 



ADJ (0, 1) 
(SAVE RETURNED VALUE) 



OBTAIN 

RCW 
AT (F+ 1) 



SETUP 

REGISTERS TO RETURN 

TO PRIOR PROCEDURE, 

SAVE BOSR AND CUT 

BACK THE STACK 




YES 




OBTAIN WORD 
ADDRESS 

BY(F) 



OBTAIN PREVIOUS 

MSCW AND 

SAVE ADDRESS 




YES 




-fcHECKITJ 



COMPUTE ADDRESS 

OF PREVIOUS 

MSCW AND 

SAVE VALUE BIT 





OBTAIN NEW 

STACK 

AND SAVE 

ADDRESS INFO 



UPDATE QJI 
AND OBTAIN 
NEW MSCW 



OBTAIN SEG. DESC. 

ADDRESSED BY PDR 

SET PBRTO ADDRESS IN 

S.D. & CAUSE FETCH 





GO TO EVAL 
OPERATOR 

& 
SET "T" REG. 
TO VALC OP. 



NO 



OPER. 
COMPLETE 



Figure 7-4. Flow of Return Operator 



7-38 



[ENTER j 

V 

ADJ (0, 0) 

AND OBTAIN WORD 

ADDRESSED BY 

(F+l) 




STUFFED 



NORMAL 




NO 




OBTAIN WORD 

ADDRESSED BY 

IRW 



NO 




YES 



OBTAIN NEW 
PROGRAM 
STACK 



SAVE OFF PRESENT 
REGISTER SETTINGS 

(RCW) 



DISTRIBUTE 

PCW 

REGISTER SETTINGS 



STORE 
RCW AT 
(F+D 



OBTAIN 

MSCW 

AT 

(F) 



COMPLETE THE MSCW 

AND STORE IT BACK 

AT(F) 



OBTAIN WORD 

ADDRESSED BY 

NEW PDR 




NO 




PLACE PROGRAM 

ADDRESS IN 

PBR AND FORCE 

A FETCH 



OPER. 
COMPLETE 



Figure 7-5. Flow of Enter Operator 



7-39 



An indexed Data Descriptor is left in the A register when the tar- 
get is referenced by an indexed Data Descriptor; a stuffed Indir- 
ect Reference Word is left in the A register when the target is 
referenced by Indirect Reference Words. 

If the A register does not contain a Data Descriptor or an Indir- 
ect Reference Word at the start of this operator an invalid operand 
interrupt is set and the operation is terminated. 

MARK STACK OPERATOR (MKST) AE. 

This operator places a Mark Stack Control Word in the B register 
containing a pointer to the previous Mark Stack Control Word in 
the stack. It adjusts the stack to push the MSCW into Memory. 

This operator is used to mark the stack when entry into a procedure 
is anticipated. 

STUFF ENVIRONMENT (STFF) AF . 

This operator changes a normal Indirect Reference Word to a stuffed 
Indirect Reference Word so that a quantity may be referenced from 
a different addressing environment. The displacement field locates 
the MSCW below the quantity and the index field locates the quan- 
tity relative to the MSCW. Figure 7-7 shows a simplified flow 
chart of the Stuff Environment operator. 

If the word in the A register at the start of the operator is not 
an Indirect Reference Word an invalid operand interrupt is set 
and the operation is terminated. 

If when creating this stuffed IRW other than a MSCW is accessed a 
sequence error interrupt is set and the operation is terminated. 

INSERT MARK STACK OPERATOR (iMKS) CF . 

This operator builds a Mark Stack Control Word and places it below 

the two top-of- stack quantities. 



7-^0 




EVAL 



ADJ (1 , 2) 




NO 




MARK DESCRIPTOR 

AS A COPY AND 

SAVE IT IN THE 

"A" REGISTER 



OBTAIN WORD 

ADDRESSED BY 

IRW 



YES 



OBTAIN WORD 

ADDRESSED BY 

SIRW 



OPER. 
COMPLETE 




NO 




OBTAIN WORD 

ADDRESSED BY 

SIRW 



Figure 7-6. Plow of Evaluate Operator 



7-*H 







ADJ (1, 2) 




NO 




OBTAIN WORD 
ADDRESSED 

BY 
"D" REGISTER 




NO 




SAVE 

MSCW 

STACK 

NUMBER 




NO 



OBTAIN 
STACK VECTOR 
DESCRIPTOR AT 
DO + 2 



YES 




COMPUTE DISP. FIELD 

SET LL FIELD TO ZERO 

AND MARK IRW 

AS STUFFED 



OPER. 
COMPLETE 



Figure 7-7. Flow of Stuff Environment Operator 



7-42 



SECTION 8 
VARIANT MODE OPERATION AND OPERATORS 

GENERAL . 

The Variant Mode of operation extends the number of operation codes. 

These operators are not used as often and require two syllables j 
the first is the "Escape TO 16 Bit Instruction" (VARl) operator. 

When the VARI operator is encountered the following syllable is 

the actual operation and the syllable pointer is positioned beyond 

the two syllables. The VARI operator is valid only for the syl- 
lables covered in this section. 

Variant codes EO thru EF are detected and cause a programed op- 
erator interrupt. All other unassigned variant codes cause no 
action and result in a loop timer interrupt. 

Variant Mode operations are both word and string- oriented operators. 

OPERATORS . 

SET TWO SINGLES TO DOUBLE (JOIN) 95^2. 

The operands in the A and B registers are combined to form a double- 
precision operand that is left in the B and Y registers. 

The operand in the A register is placed in the Y register. The A 
register is marked empty and the B register tag field is set to 
double- precis ion. 

SET DOUBLE TO TWO SINGLES (SPLT) 95^3- 

The SP(DP) operand in the B register is changed to two single-pre- 
cision operands which are placed in the A and the B registers, both 
registers are marked full. 

If the operand in the B register is a single operand, the A register 
is set to zero and the A and B registers are marked full. Both the 
A and the B register tag fields are set to single-precision. 



-1 



If the operand, in the B register is a double-precision operand the 
Y register operand is placed in the A register and the tag fields 
of both the A and B registers are set to single-precision. 

IDLE UNTIL INTERRUPT ( IDLE ) 9544. 

This operator suspends processor program execution until restarted 
by an external interrupt. IIHF is reset to allow external inter- 
rupts . 

SET INTERVAL TIMER (SINT) 95^5- (Control State Oper. ) 
This operator places the 11 low-order bits of the B register into 
the Interval Timer register, and arms the timer. The Interval 
Timer decrements each 512 microseconds,- interrupting the proces- 
sor when it reaches zero and is still armed. The Interval Timer 
is disarmed when the processor is interrupted by an external inter- 
rupt . 

The operand used to set the Interval Timer is integerized before 
the 11 low-order bits are used. If the operand can not be integer- 
ized an integer overflow interrupt is set and the operation is 
terminated . 

ENABLE EXTERNAL INTERRUPTS (EEXl) 9546 . 

This operator causes the processor to enter normal state allowing 
it to respond to external interrupts. This is accomplished by 
setting the Normal-Control State (NCSP) and the Interrupt Inhibit 
(IIHF) flip flops to zero. 

DISABLE EXTERNAL INTERRUPTS (DEXl) 9547. 

This operator causes the processor to ignore external interrupts. 
This is accomplished by setting the Interrupt Inhibit flip flop to 
one and entering control state. 

SCAN OPERATORS. 



The Scan operators communicate between the processor and the I/O 
Data Com. , or General Control Subsystems via a two section scan bus 
One section consists of 32 address and control lines and the other 
section, 48 data lines. The Scan-In functions read information 



8-2 



from the subsystem to the top of stack register in the processor. 
The Scan-Out functions write information from the top of stack 
registers in the processor to the subsystem. 

Parity is checked during transmission of both address and infor- 
mation, and a SCAN-BUS parity error interrupt is generated if the 
check fails. 

READ TIME OF DAY CLOCK. 

This operation transfers the time-of-day register from the multi- 
plexor to the B register. It is important to note that if the 
system has multiple multiplexors only one time-of-day clock is 
active. MPX A responds when a multiplexor is not designated. 

As this operation is initiated, the A register contains the code 
word shown in figure 8-1. 












°19 




15 



11 




°7 




3 




°50 




18 




14 




10 


1 

6 


2 






49 




17 




13 



9 


1 
5 


1 






48 




16 




12 




°s 




4 




°0 



Figure 8-1. Read Time-Of-Day Code Word 

The time-of-day word resulting from this operation is shown in 
figure 8-2. The B register is marked full and the A register is 
marked empty at the completion of this operation. 







— 


:•:•;!&' 


35 


31 


27 


23 


19 


15 


11 


7 


3 



50 


34 


30 


26 


22 


18 


14 


10 


6 


2 




49 


33 


?? 


?5 


AE OF DXY 
?li 17 13 


9 


5 


1 




48 


32 


28 


24 


20l 16 


12 


8 


4 






Figure 8-2. Time of Day Word 



8-3 



READ GENERAL CONTROL ADAPTER. 

This operation places the contents of one of the three general con- 
trol registers into the B register. Figure 8-3 shows the format 
of the function code word that is present in the A register as the 
operation is initiated. 



50 



49 



48 PJJ i 



19 



18 



17 



16 



15 



14 



13 



12 



11 



10 



9 ; 



4 ill 



Z. 



z. 



Figure 8-3. Read General Control Adapter Code Word 
There are four General Control designations: 



a . 


Z 


= 0001, 


GCA 


A 


b. 


Z 


= 0010, 


GCA 


B 


c . 


Z 


= 0100, 


GCA 


C 


d. 


Z 


- 1000, 


GCA 


D 



a. 


N 


= 00, 


b. 


N 


= oi, 


c . 


N 


= 10, 


d. 


N 


= 11, 



The N field can address or read one of four, 48-bit general control 
adapter registers. The registers and their addresses are: 

Input Register. 
Interrupt Mask. 
Interrupt Register. 
Output Register. 

The A register is marked empty, the B register contains the word 
read from the general control adapter and is marked full as this 
operation is completed. 

READ RESULT DESCRIPTOR. 

This operation places a result descriptor into the B register from 
the multiplexor specified. The A register contains the code word 
shown in figure 8-4. 



8-4 













19 



15 




11 






7 


•:•:•:•:•:• 



3 






50 


;0 

; 18 



14 



10 


1 
6 


Z 
2 




°49 


!°17 


°13 


°9 


°5 


Z 
1 




°48 


:0 

! 16 



12 






8 




z 

4 




1 




Figure 8-4. Read Result Descriptor Code Word 
Multiplexor designations are: 

a. Z = 0001, MPX A 

b. Z = 0010, MPX B 

At the completion of this operation the B register contains the re- 
sult descriptor shown in figure 8-5* The B register is marked full 
and the A register is marked empty. The result is not defined if 
the multiplexor has no result descriptor. 





. ■ : 


47 


43 


39 


35 


31 




C.C. 
27 


'■.\. : ':\':':'.': 


U.N. 
23 


U.N. 
19 




1 15 


11 


7 


3 




50 


46 


42 


38 


34 


30 


C.C. 
26 


U.N. 
22 


U.N. 
18 


i 14 


10 


6 


2 




49 


45 


MEMORY ADDRESS 
41 37 33 29 


C.C. 
25 


U.N. 
21 


U.N. 
17 


ERROR FIELD 
i 13 9 5 1 



48 


44 


40 


36 


32 


28 






U.N. 
24 


U.N. 
20 




Id 


> 12 


8 


4 






Figure 8-5. Result Descriptor 

The result descriptor error field is divided into a standard error 
field and unit error field. The unit error field bit assignments 
are defined individually for each peripheral control: 



Exception. 
Attention. 
Busy. 

Not ready. 
Descriptor Error. 
Memory Address 
Memory Parity Error 
Bit 16, Memory Protect. 



a . 


Bit 


o, 


b. 


Bit 


1, 


c . 


Bit 


2, 


d. 


Bit 


3, 


e . 


Bit 


4, 


f . 


Bit 


5, 


g- 


Bit 


6, 


h. 


Bit 


16 



8-5 



The "U.N." field in figure 8-5 is the unit number field. The "C.C." 
field is the character count field. 

READ INTERRUPT MASK. 

This operation places the interrupt mask word into the B register 
from the multiplexor specified. The A register contains the code 
word shown in figure 8-6. 












19 



15 



1 


L-.'l 


1 

7 


:•:• 





3 




°50 


°>8 



14 


°io.M: 


°6 


Z 
2 




°49 


°,7 



13 




!' 9 



5 


Z 
1 





48 



16 



12 


! 
8 


Hiiiii 

4 




1 




Figure 8-6. Read Interrupt Mask Code Word 



a. 
b. 



Z = 0001, MPX A 



Z = 0010 



MPX B 



The B register contains the interrupt mask word as shown in figure 
8-7 at the completion of this operator. The B register is marked 
full, the A register is marked empty. 



°50 


49 


48 


:j:;;;: ; :- 








7 


3 


6 


2 




'i'i'i'i; 


9 


5 


1 


8 


4 






Figure 8-7. Interrupt Mask Word 



The mask bit assignments are: 

a. Bit 0, Status Change. 

b. Bit 1, D.C.P. - 1. 

c. Bit 2, D.C.P. - 2. 

d. Bit 3, D.C.P. - 3. 



i-6 



e. Bit k, D.C.P. - k. 

f. Bit 9, I/O finished. 

The bit is set in the interrupt mask if recognition of the inter- 
rupt is inhibited. 

READ INTERRUPT REGISTER. 

This operation places an interrupt register word into the B regis^ 
ter from the multiplexor specified. The A register contains the 
code word shown in figure 8-8. 












19 



15 




11 




1 
7 





3 

Z. 

2 
Z. 

1 






50 


49 

°48 




1§ 




14 



10 




6 





17 



13 





9 



5 





16 



12 



8 





4 




M 



a. 
b. 



Figure 8-8. Read Interrupt Register Code Word 

Z = 0001 MPX A 
Z = 0010 MPX B 



The B register contains the interrupt register word as shown in 
figure 8-9 at the completion of this operation and is marked full, 
the A register is marked empty. 



50 



49 



48 



INT. REGISTER 



_5_ 



Figure 8-9. Interrupt Register Word 



,-7 



The interrupt register bit assignments are: 



a . 


Bit 


o, 


Status 


Change 


b. 


Bit 


1, 


D.C.P. 


- 1. 


c . 


Bit 


2, 


D.C.P. 


- 2. 


d. 


Bit 


3, 


D.C.P. 


- 3- 


e . 


Bit 


4, 


D.C.P. 


- 4. 


f . 


Bit 


9, 


I/O Finish. 



The bit is set in the Interrupt Status Register if the interrupt is 
pending . 

READ INTERRUPT LITERAL. 

This function places the interrupt literal word into the B register 

from the multiplexor specified. The A register contains the code 

word shown in figure 8-10. 





Si 








19 




15 


11 




1 
7 





3 




o 

50 




18 




14 




10 


1 
6 


Z. 
2 





49 




17 




13 




9 


1 
5 


Z. 

1 




°48 



16 



12 




1 
8 





4 




1 




Figure 8-10. Read Interrupt Literal Code Word 



Multiplexor designations are 

a. Z = 0001 MPX A 

b. Z = 0010 MPX B 



At the completion of this operation the B register contains the 
interrupt literal word as shown in figure 8-11 and is marked full 
the A register is marked empty. 



50? 



49 



48 



NTERRUPT 
W 2 



LITERAL 
5 1 



Figure 8-11. Interrupt Literal Word 
The interrupt literal bit assignments are: 

a. Bits 3(*0, ° 001 = MPX A - 

0010 = MPX B. 



b. Bits 7 W , ° 001 

0010 
0011 
0100 
1001 
1111 



D.C.P. - 1. 

D.C.P. - 2. 

D.C.P. - 3- 

D.C.P. - k. 

Multiplexor I/O finished 

Status Change. 



INTERROGATE PERIPHERAL STATUS. 

This operation places one of eight possible status vector words 
into the B register from one of the multiplexors. A B 65OO may 
have up to 256 peripheral units designated in the system. This 
configuration requires eight status vector words, each indicating 
the ready status of 32 units. Vector word interrogates the status 
of units through 31, vector 1 the status of units 3^-63, etc. 
The A register contains the code word shown in figure 8-12. 













19 




15 


; - ; 


N. 

11 






7 





3 


; : : 



50 



18 



14 


N. 
10 



6 


Z. 
2 




49 







17 



13 


N. 
9 


1 

5 


Z. 
1 



48 





16 



12 







8 





4 


v.v.v.v.yA 


M. 




Figure 8-12. Interrogate Peripheral Status Code Word 



8-9 



Multiplexor designations are: 



a. Bit ; M 

M 

b. Bit 4(4) ; Z 

Z 



0, All multiplexors are to respond. 

1, Multiplexor designated by Z to respond 

0001 MPX A 
0010 MPX B 



c. Bits 11(3), N = Status vector number, thru 7. 

At completion of this operation, the B register contains the status 
vector word addressed by the value of N with the status vector word 
in a format shown in figure 8-I3. The B register is marked full 
and the A register is marked empty. 



































:•:•!•:•:•:•: 


31 


27 


23 


19 


15 


11 


7 


3 











STATUS BITS 






$0 








30 


26 


22 


18 


14 


10 


6 


2 























49 










29 


25 


21 


17 


13 


9 


5 


1 



























W$M x . 


48 


: : : ; : :i:i;i:i 






32 


28 


24 


20 


16 


12 


8 


4 








Figure 8-13. Status Vector Word 

A status-change bit is assigned to each line printer or display 
unit and indicates completion of paper-motion or input request. 

The X bit in the status vector word is on if the word is valid. 

INTERROGATE PERIPHERAL UNIT TYPE. 

This operation places the peripheral unit type word into the B 
register from one of the multiplexors. The A register contains the 
code word shown in figure 8-14. 



8-10 







.. 





19 




15 


11 




1 

7 





3 


811:88 




50 




18 


UNIT 
14, 10 


1 
6 


Z. 
2 



49 



17 


NUMBER 
13 9 



5 


Z. 

1 



48 






16 


12 






8 





4 




M. 




Figure 8-l4. Interrogate Peripheral Unit Type Code Word 

a. M = 0, All multiplexors to respond. 

b. M = 1, Multiplexor designated by Z respond. 
When M = 1, the Z field MPX designations are: 

a. Z = 0001, MPX A. 

b. Z = 0010, MPX B. 

Upon completion of this operator the B register contains the peri- 
pheral unit type word as shown in figure 8-15 and is marked full? 
the A register is marked empty. 



50 



A3. 



48 



T.C. 
5 



T.C. 
4 



T.C. 
3 



T.C, 



2. 



T.C, 



T.C. 




Figure 8- 15. Unit Type Code Word 



The following codes identify the units 



Code 



Unit 



a . 


00 


b. 


01 


c . 


02 


d. 


Ok 



No unit. 

Disk File. 

Display. 

Paper- Tape Reader 



8-11 



Code 



Unit 



e . 


05 


f . 


06 


g- 


07 


h. 


09 


i . 


OB(ll) 


3 • 


0D(13) 


k. 


0E(l4) 


1. 


of(15) 


m. 


1D(29) 


n. 


IE(30) 


o . 


1F(31) 


P. 


26(38) 


q- 


27(39) 



Paper-Tape Punch . 

Buffered, Line- Printer I, BCL Drum. 

Unbuffered, Line- Printer , BCL Drum. 

Card Reader. 

Card Punch. 

Magnetic Tape(7 track). 

Magnetic Tape (9 track N.R.Z.). 

Magnetic Tape (9 track P.E.). 

Magnetic Tape (7 track) . 

Magnetic Tape (9 track N.R.Z.) 

Magnetic Tape (9 track P.E.). 

Buffered Line-Printer, EBCDIC- subset drum. 

Unbuffered Line- Printer , EBCDIC- subset drum. 



With status 
vector in- 
formation. 

No status 
vector in- 
formation . 



INTERROGATE I/O PATH. 

This operation determines the availability or absence of an access 
to a specified unit. The result word is placed in the B register. 
The A register contains the code word shown in figure 8-16. 













: 















0„ 














19 




15 


11 




7 




3 




! 


= 


UNIT 





Z. 


50! 










18 




14| 10 


lijijijijijili 


6 




2 





49; 


! o 

17 


NUMBER 
13 9 




5 


Z. 

1 


j 
48: 




16 


12 





8 





4 




M. 




Figure 8-16. Interrogate I/O Path Code Word 
Primary Multiplexor designations are: 

a. M = 0, All multiplexors respond. 

b. M = 1, Multiplexor designated by Z to respond. 



1-12 



Multiplexors designations with M=l are: 

a. Z = 0001, Multiplexor A. 

b. Z = 0010, Multiplexor B. 

At the completion of this operation the B register contains the 
result word shown in figure 8-17 and is marked full*, the A reg- 
ister is marked empty. 








































19 




!; '5 


11 




7 




3 


: 








UNIT 





z. 


50 








18 




14, 10 




6 




2 


: 








!! NUMBER 





z. 


49 








17 




13 9 




5 




1 


' .: 

























A. 


48 






•r".* ••:•*:■:• i*:!:*:*: 1 :*.** 


Id 


> 12 


:::•:■:::•::: 


8 


■ ■•■'■■'■'■:':■':: 


4 


•■■•■■■••'■■•I- 






Figure 8-17 . I/O Path Result Word 
The A bit indicates path availability: 

a. A = 0, No path available. 

b. A = 1, Path is available. 

The Z field identifies the multiplexor when a path is available: 

a. Z = 0001, Path is via multiplexor A. 

b. Z = 0010, Path is via multiplexor B. 

A data channel consists of a data switching channel and a peri- 
pheral control. 

SCAN OUT (SCN0) 95^B. 

Scan Out places bits 0-19 of the top-of-stack word on the scan-bus 
address lines, and the second stack word on the scan-bus informa- 
tion lines. An Invalid Address interrupt results if the address- 
word is invalid. The A and B registers are empty upon successful 
completion of a Scan-Out. 



8-13 



SET TIME OF DAY CLOCK. 

This operation transfers the time of day information from the B 
register to the time of day register in the multiplexor (figure 8-I9) 
The code word shown in figure 8-18 is in the A register. MPX A 
responds when a multiplexor is not designated. An invalid- operand 
interrupt results if the processor is not in control state. 

At the completion of this operation the A and B registers are 
marked empty. 





BIB 








19 



15 



11 


; 



7 


.Y.Y.Y.Y.Y.*, 


3 


WMM 



50 



18 



14 



10 


1 
6 


2 



49 



17 



13 



9 


1 
5 


1 



48 



16 



12 





8 




4 









Figure 8-18. Set Time of Day Clock Code Word 





Iv.-iv'.VV.-A 






35 


31 


27 


23 


19 


15 


11 


7 


3 



50 


34 


30 


26 


22 


18 


14 


10 


6 


2 



49 


33 


29 


25 


TIME OF DAY 
21 17 13 


9 


5 


1 



48 


32 


28 


24 


20 


16 


12 


8 


4 






Figure 8-I9. Time of Day Word 

SET GENERAL CONTROL ADAPTER. 

This operation sets one of three addressable general control adap- 
ter registers from the word in the B register. The three general 
control adapter registers that can be set are the output register, 
interrupt mask register and the interrupt register,, 



8-14 



The A register contains the code word shown in figure 8-20 and the 
B register contains the output, the interrupt mask or the interrupt 
word . 





.;.:.;■!■;.;. 






1 










1 




Z. 


: 










19 


15 


11 






7 




3 















N. 







Z. 


50 








18 


14 




10 




6 




2 















N. 


1 


Z. 


49 








17 


13 




9 




5 




1 






















Z. 




1 


48 


: i : i : i : i : ; : ;l 






16 


12 




8 




4 


••:J:«:I:*:' 






Figure 8-20. Set General Control Adapter Code Word 
Multiplexor designations are: 

a. Z = 0001, MPX A. 

b. Z = 0010, MPX B. 

Output, interrupt, or interrupt mask register designations are: 

a. N = 00, Output. 

b. N = 01 , Interrupt mask register. 

c. N = 10, Interrupt register. 

At the completion of this operator both the A and B registers are 
marked empty. 

INITIATE 1/0. (Control State Only). 

This operation initiates an 1/0 unit specified by the code word 

in the A register. The code word format is shown in figure 8-21. 














50 







49 







48 






























WM 


•iSSiv/S 


19 




15 


11 






7 






3 


W$m 














Z. 




/■.■ : :V-;-i 


18 




14 


10 






6 






2 


vXvX'Sv 



17 


v 


13 


9 



5 


Z. 


1 


:■■'.':;'■;■':;:; 




16 


12 







8 





4 






1 





Figure 8-21. Initiate 1/0 Code Word 



8-15 



The B register holds the area descriptor and has the format shown 

in figure 8-22. The area descriptor points to the base address 

of the I/O area where the I/O control word is located (figure 8-23) 

At completion of this operator the A and B registers are marked 
empty. 









































39 


35 


31 


27 


23 




19 


15 


11 


7 


3 







BUFFEF 








AREA 




50 i 








38 


34. 30 


26 


22 




18 


14. 10, 6 


2 







LENGTH 






1 ' 
BASE ADDRESS 




49 i 








37 


33 29 


25 


21 




17 


13 9 5j 


1 

























48 | 


-'•-'•'■'•'•'••'' 






36 


32 


28 


24 


20 

_ 




16 


12 


8 


4 






Figure 8-22. Area Descriptor 

The I/O control word pointed to by the area descriptor is trans- 
ferred to the multiplexor. It is divided into a standard control 
field and a unit control field. The unit control field bit assign- 
ments are defined individually for each control: 







47 


43 


39 









STANDARD 


50 




46 . 42 . 38 









1 1 
CONTROL 


49 




45, 41. 37 









1 1 
FIELD 


48 


!v>>>>>Xv>X\ 


44 1 40 1 36 


'■•■"■ViYiYiYi'i 






Figure 8-23- I/O Control Word 



8-16 



Bit Assignment Bit=0 Bit=l 



a 



47, Reserved 

b . 46, Reserved 

c. 45, Attention No Yes 

d. 44, Read/write write read 

e. 43, Memory Inhibit No Yes 
f« 42, Translate No Yes 
£• **!, Frame length 6-bit 8-bit 
h» 40, Memory protect No Yes 
i« 39? Backward transfer No Yes 
J« 38, Test No Yes 
k. 37-36, Tag field transfer 37=1 36=0 
!• 37-36, Store program tag 37=0 36=1 
m. 37-36, Store single-precision tag 37=0 36=0 
n. 37-36, Store double-precision tag 37=1 36=1 

READ PROCESSOR IDENTIFICATION (WHOl) 954E. 

This operator places in the A register a single-precision operand 
containing the value of the processor ID register. The register is 
marked full. 

INTERRUPT OTHER PROCESSOR (hEYU) 954f. 

This operator sets the processor interrupt register of the other 

processor . 

OCCURS INDEX (OCRX) 9585. 

This operator places in the B register a new index value calculated 
from the Index Control Word (iCW) in the A register (figure 8-24) 
and the operand in the B register (figure 8-25). 



8-17 







47 


43 


39 


35 


:&&££ 


31 


27 


23 


19 


IMlWiy.l.TT 

'•••••••••••••••'•v.Vt 


15 


11 


7 


3 



50 


46 


42 


38 


34 


30 


26 


22 


18 


14 


10 


6 


2 



49 


45 


■ ■ * 

LENGTH 
41 37 


33 


29 


SIZE 
25 


21 


1^ 


13 


OFFSET 
9 5 


1 



48 


44 


40 


36 


32 


28 


24 


20 


16 


12 


8 


4 






Figure 8-24. Index Control Word 







47 


43 


39 


35 


31 


27 


23 


19 


15 


11 


7 


3 


50 


46 


42 


38 


34 


30 


26 


22 


18 


14 


10 


6 


2 


49 


45 


41 


37 


33 


29 


25 


21 


17 


INDEX 
13 


9 


5 


1 


48 


44 


40 


36 


32 


28 


24 


20 


16 


12 


8 


4 






Figure 8-25* Index Word 

The index word in the B register is integerized: if the index is 
greater than the maximum integer value (5^9 , 755 , 813 » 887 ) the in- 
teger overflow interrupt is set and the operation terminated. 

The length field of the ICW is multiplied by the index value minus 
1, and that value is added to the offset field of the ICW. This 
result is the new index. The A register is marked empty and the 
B register is marked full. 

If either the ICW or the operand has a value of zero, the invalid- 
index interrupt is set and the operation is terminated. 

If the index value is less than zero or greater than the size field 
of the ICW, the invalid- index interrupt is set and the operation 
is terminated. 



■ -li 



INTEGERIZED, ROUNDED, DOUBLE- PRECISION (NTGD) 9587. 

This operator creates a double-precision, rounded integer in the 
B register from the operand in the B register. The B register is 
marked full. If the word in the B register at the start of this 
operator is not an operand, the invalid- operand interrupt is set 
and the operation is terminated. 

If the operand in the B register is larger than 8t26-l in absolute 
value, the integer- overflow interrupt is set and the operation is 
terminated . 

The B register is marked as a double-precision operand (tag bits 
set to 010) and the exponent is set to 13 . 

LEADING ONE TEST (LOG 2) 958B. 

This operator locates the most significant "one" bit of the word 
in the B register and places the location of that bit into the B 
register (bit number + l). 

If a one bit is not sensed the B register is set to zero. 

The B register is marked full. 

MOVE TO STACK (MVST) 95AF. 

This operator causes the processor's environment (or addressing 
space) to be moved from the current stack to the program stack 
specified by the operand in the B register. 

The operator builds a Top of Stack Control Word (figure 8-26) and 
places it at the base of the current stack as addressed by the Base 
of Stack Register. 

The operand in the B register is integerized and checked for in- 
valid index against the stack vector. The value in the B register 
is added to the address field of the stack vector Descriptor 
(at D[0]+2), to address the descriptor for the new stack. 



8-19 





ES 
47 














DSF 




N 
19 










°50 

1 

49 




6 
46 








LL 






T 
45 














DFF 


1 
48 






F 
44 











ES - EXTERNAL SIGN FLIP-FLOP 

O - OVERFLOW FLIP-FLOP 

T - TOGGLE, TRUE-FALSE FLIP-FLOP 

F - FLOAT FLIP-FLOP 

DSF - DELTA S-REGISTER FIELD; VALUE OF rS RELATIVE TO BOSR 

N - NORMAL-CONTROL STATE FLIP-FLOP 

LL - ADDRESSING LEVEL 

DFF - DELTA F-REGISTER FIELD; VALUE OF rF RELATIVE TO rS 

Figure 8-26. Top of Stack Control Word (TSCW) 

The Data Descriptor for the requested stack is accessed. If its 
presence bit is on, the address field is placed into the Base of 
Stack Register. The Top of Stack Control Word is brought up and 
the stack is marked "active" by storing the processor ID at the 
base of the stack. The TSCW is distributed and the D registers 
are updated. 

If during the integerization the operand in the B register is too 
large, the integer-overflow interrupt is set and the operation is 
terminated. 

If the index value is less than zero or greater than the length 
field of the Data Descriptor for the stack vector array, an invalid 
index interrupt is set and the operation is terminated. 

SET TAG FIELD ( STAG ) 95B4. 

This operator sets the tag field (bits 50:3) in the B register to 
the value of bits 2:3 of the operand in the A register. At the 
completion of the operation the A register is marked empty and the 
B register is left full. 



8-20 



READ TAG FIELD (RTAG) 95B5- 

This operator replaces the word in the A register with a single- 
precision operand equal to the tag field of that word. The tag 
bits are placed in bits 2:3. The A register is marked full. 

ROTATE STACK UP (RSUP) 95B6). 

This operator permutes the top three operands of the stack so that 
the first operand has become second, the second has become the 
third, and the third has become the first (see figure 8-27). 



BEFORE ROTATION 



AFTER ROTATION 



rA 
rB 

s- 



WORD ONE 



WORD TWO 



WORD THREE 



rA 
rB 
S- 



WORD THREE 



WORD ONE 



WORD TWO 



Figure 8-27. Stack Rotation Up 

ROTATE STACK DOWN (RSDN) 95B7 . 

This operator permutes the top three operands of the stack so that 
the first has become third, the second has become the first, and 
the third has become the second (see figure 8-28). 



rA 
rB 
S- 



BEFORE ROTATION 



WORD ONE 



WORD TWO 



WORD THREE 



AFTER ROTATION 



rA 


WORD TWO 


rB 


WORD THREE 


s— 


WORD ONE 

— -I 



Figure 8-28. Stack Rotation Down 



S-21 



READ PROCESSOR REGISTER (RPRR) 95B8. 

This operator reads the contents of one of the eight Base registers, 
eight Index registers or one of the 32 D registers into the A 
register . 

The six low order bits of the A register selects the processor reg- 
ister to be read. 

The decoding of these six bits is as follows: 

a. Bits 5 & 4 = 10 = Index Register 

b. Bits 2:3 = 0, = PIR 



= 1, 


= SIR 


= 2, 


= DIR 


= 3, 


= TTR, BUF3 


= 4, 


= TOSR 


= 5, 


= BOSR 


= 6, 


= P 


= 7, 


= BUF 



c. Bits 5 & 4 = 11 = Base Register 

d. Bits 2:3= 0, = PBR 



= 


1, 


- 


IBR 


= 


2, 


= 


DBR 


= 


3, 


= 


TBR, BUF 2 


= 


4, 


= 


S 


= 


5, 


= 


SNR 


= 


6, 


= 


PDR 


= 


7, 


= 


TEMP 



If Bit 5 is zero, bits 4:5 select the D register equal to the 
binary value of the bits. (i.e., Bits 4:5 = 00101 selects D reg- 
ister 5 • ) 



8-22 



The A register at the completion of this operation contains the 
contents of the register that was selected and is marked full. 

SET PROCESSOR REGISTER (SPRR) 95B9 • 

This operator places the contents of the address field of the A 
register into one of the eight Base registers, eight Index regis- 
ters or 32 D registers selected by the six low-order bits of the 
word in the B register. 

The decoding of the six bits is the same as in the Read Processor 
Register operator. 

The A and B registers are marked empty. 

READ WITH LOCK (RDLK) 95BA. 

This operator performs the same operation as the Overwrite opera- 
tor (see section 7) with the exception that the word which was in 
memory before the overwriting is left in the B register. 

COUNT BINARY ONES (CBON) 95BB. 

This operator counts the number of one bits in the S.P.(D.P.) op- 
erand in the A register. At the completion of the operation the 
total count is left in the A register with the register marked full. 

LOAD TRANSPARENT (LODT) 95BC. 

This operator performs a Load operator (see section 7) if the word 
in the A register is a Data Descriptor or an Indirect Reference Word 
If it is not either of these, bits 19:20 of the A register are used 
as the address to bring an operand to the A register. Copy bit 
action does not occur. 

LINKED LIST LOOKUP (LLLU) 95BD. 

This operator searches a linked list of words. 

The operator starts with an operand in the top of the stack as the 
index pointer. The second word in the stack is a non- indexed Data 
Descriptor to the array containing the linked list. The third word 
in the stack is an operand that is the argument. 

8-23 



The base address of the linked list, the length of the list and 
the argument value are saved throughout the entire operator process 

The word addressed by the base address plus the index value is read 
and checked for a value of zero in the address (Link) portion of 
the word (zero denotes the end of the linked list). If the link 
is non-zero, bits k7 : 28 are compared to the argument value. If 
the argument of the linked- list word is less than the argument 
value, the actions of this paragraph are repeated using the link as 
the new index. 

When the value of the argument field of the linked- list word is 
equal to or greater than the argument value the operation is com- 
plete. The index pointing to the word whose link points to the 
argument which satisfies the test is left in the A register and is 
marked full . 

If the value of the link portion of the linked list word is equal 
to zero, the A register is set to minus one (-l), and marked full 
as the operation is completed. 

If the index value in the linked list word is greater than the 
length value from the descriptor, an invalid index interrupt is 
set and the operation is terminated. 

When the first word in the stack at the start of this operator is 
not an operand an invalid- operand interrupt is set and the opera- 
tion is terminated. 

If the Data Descriptor has been indexed, the invalid- operand inter- 
rupt is set and the operation is terminated. 

MASKED SEARCH FOR EQUAL (SRCH) 95BE. 

At the start of this operator the word in the A register must be a 
Data Descriptor. The operand in the B register is a 51 bit mask. 
The Data Descriptor in the A register and the mask in the B regis- 
ter are saved and the 51 bit argument word is placed into the B 



8-24 



register. If the descriptor is indexable (bit k$ equal to zero), 
the index bit (bit k$) is set and one is subtracted from the length 
field. If bit k$ is equal to one the data descriptor is already 
indexed, therefore, that index is the starting value. 

The word addressed by the descriptor is placed in the A register 
and ANDed with the mask word. The result of this AND function is 
tested to determine if it is identical to the argument word. 

If the comparison is not equal the index field of the descriptor 
is decreased by one and the operation is repeated. If the index 
field is equal to zero, the A register is set to a minus one value 
and marked full. The B register is marked empty. 

If an equal comparison is made, the A register contains the index 
pointing at the last word compared and is marked full. The B 
register is marked empty. 

UNPACK ABSOLUTE, DESTRUCTIVE (UABD) 95D1. 

This operator unpacks a string of 4-bit digits into 6-bit characters 
or 8-bit bytes. At the start of the operator the word in the A 
register defines the length of the operand in the B register which 
is the string of digits to be unpacked. 

The third word in the stack is a string descriptor addressing the 
destination of the string. 

As the specified number of digits are transferred to the destination, 
zone fill is as follows: 

a. If the destination size is 6 bits (BCL) , the characters are 
transferred to the destination with the two zone bits set 
to zero. 

b. If the destination size is 8 bits (EBCDIC) the bytes are 
transferred to the destination string with the four zone 
bits set to 1111. 



c 



If the destination size was 0, it is set to 8-bits and 
handled as in (b ) above. 

8-25 



UNPACK ABSOLUTE, UPDATE (UABU) 95D9. 

This operator performs an Unpack Absolute operation, and at the 
completion of the operation, the destination pointer is updated 
and left in the stack. 

UNPACK SIGNED, DESTRUCTIVE (USND) 95DO. 

This operator performs an Unpack operation, with an added function, 
if the External Sign flip flop is set then a zone of 10 is set in 
the last character for 6-bit or a zone of 1101 is set in the last 
byte for 8-bit. 

If the destination size is 4-bit, the first digit position of the 
destination string is set to 1101 if the External Sign flip flop 
is set. If the External Sign flip flop is zero the first digit 
is set to 1100. 

UNPACK SIGNED, UPDATE (USNU) 95D8. 

This operator performs an Unpack Signed operation., and at the com- 
pletion of the operator, updates the destination pointer. 

TRANSFER WHILE TRUE, DESTRUCTIVE (TWTD) 95D3 . 

This operator transfers characters from the source string to the 
destination string for the number of characters specified by the 
length operand while the stated relationship is met. If the rela- 
tionship is not met the transfer is terminated at that point. The 
relationship is determined by using the source character to index 
a table. If the bit indexed is a one the relationship is true. 

The operator uses the top four words in the stack to set up regis- 
ters . 

The stack words are used as follows: The top word addresses the table; 
the second word is the length of the string to be transferred; the 
third word in the stack is an operand or a descriptor, addressing 
the source string or a single-precision operand which is the source 
string? the fourth word in the stack is a descriptor pointing at 
the destination string. 



8-26 



Tlie table is indexed as follows to obtain the decision bit: 
The source character is expanded to eight bits, if necessary, by 
appending- two or four leading zero bits. The three high- order bits 
of these eight select a word from the table, indexing the table 
pointer. The remaining five bits of the expanded source character 
select a bit from this word by their value. 

TRANSFER WHILE TRUE, UPDATE (TWTU) 95DB. 

This operator performs a Transfer While True operation and updates 

the source pointer, the destination pointer and repeat count. 

If all the characters specified by the length field are transferred, 
the True/False flip flop is set to one (true); otherwise, it is 
set to zero (false). 

TRANSFER WHILE FALSE, DESTRUCTIVE (TWFD) 95D2. 

This operator performs a Transfer While operation testing for a 

zero bit in the table. 

TRANSFER WHILE FALSE, UPDATE (TWFU) 95DA. 

This operator performs a Transfer While False operation, updating 
the source pointer, the destination pointer, and the repeat count. 

If all the characters specified by the length field are transferred, 
the True/False flip flop is set to one (true); otherwise, it is set 
to zero (false). 

TRANSLATE (TRNS) 95D7 • 

This operator translates the number of characters specified as they 

are transferred from the source string to the destination string. 

The translation uses a table containing the translated characters. 
The word in the top of the stack is a descriptor that addresses 
the translation table. The second operand in the stack specifies 
the length of the string. The third word in the stack is a des- 
criptor addressing the source string (or an operand which is the 
source string) and the fourth word in the stack is a descriptor 



1-27 



addressing the destination string. The source and destination are 
updated at the end of the operation. 

The translation occurs as follows: The specified string character 
is used as an index into the table to locate a character. The 
located character is transferred to the destination string. 

The least significant 32 bits of each table word provide 4 eight 
bit characters. The table sizes are as follows: 

a. 4-bit digits provide a 4 word table length. 

b. 6-bit characters provide a 16 word table length. 

c. 8-bit bytes provide a 64 word table length. 

SCAN WHILE GREATER, DESTRUCTIVE (SGTD) 95F2. 

This operator scans a string while the characters in the source 
string are greater than a delimiter character; or until the num- 
ber of characters specified have been scanned. 

At the completion of this operator if all the characters have been 
scanned the True/False flip flop is set to one. If the scan was 
stopped by the delimiter test before the end of the string the True/ 
False flip flop is set to zero. 

At the start of this operator the delimiter character is right 
justified in the top word of the stack. The length of the string 
to be scanned is the second word of the stack. The source pointer 
is the third word in the stack. 

If the second word in the stack is a descriptor, it is the source 
pointer and the length of the character string is set to 1,048,575- 

SCAN WHILE GREATER, UPDATE (SGTU) 95FA. 

This operator performs a Scan While Greater operation, and updates 
the count and the source pointer. The updated source pointer lo- 



8-28 



cates the character that stopped the scan. The number of characters 
not scanned is placed in the A register, and the register marked 
full. 

SCAN WHILE GREATER OR EQUAL, DESTRUCTIVE (SGED) 95F1. 

This operator performs a Scan While operation while the characters 

in the source string are equal to or greater than the delimiter 

character. 

SCAN WHILE GREATER OR EQUAL, UPDATE (SEGU) 95F9- 

This operator performs a Scan While Greater or Equal operation and 

updates the count and the source pointer. 

SCAN WHILE EQUAL, DESTRUCTIVE (SEQD) 95F4. 

This operator performs a Scan While operation while the characters 

in the source string are equal to the delimiter character. 

SCAN WHILE EQUAL, UPDATE (SEQU) 95FC . 

This operator performs a Scan While Equal operation and updates the 

count and the source pointer. 

SCAN WHILE LESS OR EQUAL, DESTRUCTIVE (SLED) 95F3- 

This operator performs a Scan While operation while the characters 
in the source string are equal to or less than the delimiter char- 
acter. 

SCAN WHILE LESS OR EQUAL, UPDATE (SLEU) 95FB. 

This operator performs a Scan While Less or Equal operation and 

updates the count and source pointer. 

SCAN WHILE LESS, DESTRUCTIVE (SLSD) 95FO. 

This operator performs a Scan While operation while the characters 

in the source string are less than the delimiter character. 

SCAN WHILE LESS, UPDATE (SLSU) 95F8. 

This operator performs a Scan While Less operation, and updates 

the count and the source pointer. 



8-29 



SCAN WHILE NOT EQUAL, DESTRUCTIVE (SNED) 95F5 . 

This operator performs a Scan While operation while the characters 

in the source string are not equal to the delimiter character. 

SCAN WHILE NOT EQUAL, UPDATE (SNEU) 95FD. 

This operator performs a Scan While Not Equal operation, and 

updates the count and the source pointer. 

SCAN WHILE TRUE, DESTRUCTIVE ( SWTD ) 95D5 . 

This operator uses each source character as an index into a table 
to locate a bit in the same fashion as the transfer while True 
operators. If the bit located is a one, the relationship is true 
and the scan continues. 

The first word in the stack is a descriptor addressing the table. 
The second and third words in the stack are as they are for all 
Scan While operators. 

SCAN WHILE TRUE, UPDATE (SWTU) 95DD. 

This operator performs a Scan While True operation and updates the 
count and the source pointer. The number of characters not scanned 
is placed in the A register. 

SCAN WHILE FALSE, DESTRUCTIVE ( SWFD ) 95D4. 

This operator performs a Scan While False operation, except the re- 
lation is true if the bit found by indexing into the table is zero. 

SCAN WHILE FALSE, UPDATE (SWFU) 95DC . 

This operator performs a Scan While False operation, and updates 

the count and the source pointer. 



8-30 



SECTION 9 
EDIT MODE OPERATION AND OPERATORS 

GENERAL . 

The purpose of the Edit Mode operators is to perform editing func- 
tions on strings of data. The editing functions are those which 
are normally involved in preparing information for output. They 
include such operators as Move, Insert, and Skip, in the form of 
micro-operators in either the program string or in a separate table, 
In the program string, they are single micro- operators and are 
entered by use of the Execute Single Micro or Single Pointer oper- 
ators (see section 7). If the micro- operators are in a table, the 
table becomes the program string that is to be executed. This 
table is entered by means of the Table Enter Edit operators (see 
section 7), and is exited through the End Edit micro-operator as 
defined later in this section. 

When using any of the Edit micro-operators the proper pointers must 
be in the stack. Each of the micro-operators assume that if a 
source pointer is used, a source pointer String Descriptor or the 
source string itself as an operand will be present in the stack. 
If a destination pointer is used a String Descriptor must be pre- 
sent in the stack. 

If the source or destination data has the memory protect bit (bit 
48) equal to one, the segmented-array interrupt is set and the 
current micro-operator is terminated. 

EDIT MODE OPERATORS . 

The Edit Mode operators are described in the following paragraphs 

of this section. 

MOVE CHARACTERS (MCHR) D7 . 

This micro-operator transfers characters from the source string 

to the destination string. 

If the operator was entered by the Table Enter Edit operator (see 



9-1 



section 7), the number of characters to be transferred is specified 
by the syllable following the operator syllable. 

If the operator is entered by the Execute Single Micro operator 
(see section 7), the number of characters to be transferred is 
specified by the operand in the top of the stack. 

MOVE NUMERIC -UNCONDITIONAL (MVNU) D6. 

This micro-operator transfers the four low-order bits of the char- 
acters of the source string to the destination string. If the 
destination string character size is 6 bits (BCL) the zone bits 
are set to 00. If the destination string character size is 8 bits 
(EBCDIC) the zone bits are set to 1111. 

If the operator was entered by use of the Table Enter Edit operator 
(see section 7) the number of characters to be transferred is 
specified by the syllable following the operator syllable. 

If the operator is entered by executing the Execute Single Micro 
operator (see section 7), the number of characters to be trans- 
ferred is specified by the operand in the top of the stack. 

MOVE WITH INSERT (MINS) DO. 

This micro- operator performs a Move Numeric Unconditional or an 

insert operation under the control of the Float flip flop. 

In Table Edit mode the second syllable is the repeat value and the 
third syllable is the character to be inserted under control of the 
Float flip flop. 

In Execute Single Micro mode the repeat field value is the top 
word of the stack and the insert character is in the syllable fol- 
lowing the micro- operator syllable. 

If the Float flip flop is zero and the numeric portion of the 
source characters is zero, the insert character is moved to the 
destination string. 

If the Float flip flop is zero, or if the Float flip flop is on, 

9-2 



the Float flip flop is set and the source character, with numeric 
zone, is moved to the destination. 

The number of characters transferred from the source string to the 
destination string is defined by the repeat value. 

MOVE WITH FLOAT (MFLT) Dl . 

In Table Edit mode the second syllable is the repeat value (the 
number of characters to transfer). The third, fourth, and fifth 
syllables are the three insert characters. In single-micro mode, 
the three insert characters are in the second, third, and fourth 
syllables . 

If the Float flip flop is zero and the numeric portion of the char- 
acter in the source string is zero, the first-insert character is 
transferred to the destination string. 

If the Float flip flop is zero and the numeric portion of the char- 
acter in the source string is not zero the Float flip flop is set. 
If the External Sign flip flop is a one, the second- insert charac- 
ter is transferred to the destination string. If the External 
Sign flip flop is zero the third- insert character is transferred to 
the destination string. Then the numeric version of the source 
character is transferred. 

If the Float flip flop is one the numeric equivalent of the source 
character is transferred to the destination. 

This operation continues for the number of characters defined by 
the repeat field value. 

This operator can be entered by the Execute Single Micro operator, 
with the repeat field value in the top word of the stack. 

SKIP FORWARD SOURCE CHARACTERS (SFSC) D2. 

This micro-operator increments the source pointer registers. 

If this micro-operator or any of the following Skip micro-operators 



9-3 



is entered by the execution of the Execute Single Micro operator 
the number of characters to be skipped is specifietl by the operand 
in the top of the stack. If* entry is by the execution of the 
Table Enter Edit operators, the number of characters to be skipped 
is specified by the syllable following the micro-operator syllable. 

SKIP REVERSE SOURCE CHARACTERS (SRSC) D3 . 

This micro- operator decrements the source pointer registers. 

Also see Skip Forward Source Characters micro-operator, second 
paragraph. 

SKIP FORWARD DESTINATION CHARACTERS ( SFDC ) DA. 

This micro- operator increments the destination pointer registers. 

SKIP REVERSE DESTINATION CHARACTERS ( SRDC ) DB . 

This micro-operator decrements the destination pointer registers. 

RESET FLOAT (RSTF) D4. 

This micro- operator sets the Float flip flop to zero. 

END FLOAT (ENDF) D5 . 

This micro- operator transfers the character in the second syllable 
of this operator to the destination string if the Float flip flop 
is zero and the External Sign flip flop is one. 

If the Float flip flop is zero and the External Sign flip flop is 
zero then the character in the third syllable of this operator is 
transferred . 

If the Float flip flop is equal to one, then it is reset and no 
characters are transferred. 

INSERT UNCONDITIONAL (iNSU) DC. 

This micro-operator places an insert character into the destination 
string the number of times specified by the repeat value. When 
entered by a Table Enter Edit operator, the REPEAT is in the sylla- 
ble following the micro-operator syllable, and the insert character 
is in the next syllable. 

9-4 



If this micro-operator is entered by an Execute Single Micro op- 
erator, the character to be inserted is in the second syllable and 
the repeat value is specified by the operand that is in the top of 
the stack. 

INSERT CONDITIONAL (iNSC) DD. 

This micro-operator inserts a string consisting of one of two char- 
acters into the destination. The length of the string is given by 
the repeat value from the table or the stack. 

If the Float flip flop is zero the first insert character is in- 
serted into the destination string. 

If the Float flip flop is one the second insert character is in- 
serted into the destination string. 

The insert characters follow the repeat value syllable in Table 
Enter Edit operation or the micro-operator syllable in Execute 
Single Micro operations. 

INSERT DISPLAY SIGN (iNSG) D9 . 

This micro-operator places in the destination string the character 
defined by the syllable following the micro-operator syllable if 
the External Sign flip flop is equal to one. 

If the External Sign flip flop is equal to zero this operator places 
in the destination string the character defined by the third syll- 
able of this operator. 

INSERT OVERPUNCH (iNOP) D8 . 

This micro-operator places a sign overpunch in the destination string 
character of either 10 for BCL or 1101 for EBCDIC if the External 
Sign flip flop is equal to one. 

If the External Sign flip flop is equal to zero the operator leaves 
the destination string character unaltered. 



'-5 



END EDIT (ENDE) DE. 

This operator terminates a string of Edit micro- operators in Table 

Enter Edit operation mode. 

The micro program string in the table must end with the End Edit 
operator. 



9-6 



SECTION 10 
IN PUT/ OUTPUT MULTIPLEXOR AND PERIPHERAL CONTROLS 

GENERAL. 

The internal processing speed of the B 65OO is complemented by 
equally powerful input/output (i/o) hardware to achieve a well- 
balanced computing system. Transfer of all data between memory 
and all peripheral devices is controlled by the I/O multiplexor, 
independent of the processor. One or two of these multiplexors 
may be attached to a B 65OO, each one capable of processing up to 
ten I/O operations simultaneously, from any of 28 peripheral 
devices . 

OPERATION. 



A peripheral control bus extends from the multiplexor to the 
various peripheral devices. Attached along this bus are from 
one to 20 peripheral controls (figure lO-l). Information in one 
or two-byte groups can be sent along the bus to or from any peri- 
pheral control every 1.2 microseconds. 



INPUT/OUTPUT 
MULTIPLEXOR 



DATA 

SWITCH 

CHNLS. 



CARD 
READER 



MODEL 
B 61 10 



APPROP. 

TAPE 

P.C. 






LINE 
PRINT 



MODEL 
B6240 



APPROP. 

TAPE 

P.C. 



MA 
CLUSTER 



1 TO 10 I/O 
UNITS OR SUB- 
SYSTEMS REQ . 
SMALL 
PERIPH. CONTLS. 



1 1 

1 TO 10 

PERIPH. CONTLS. 

1 TO 10 

I . L_ 



CONSOLE 
DISPLAY 
TERMINAL 
B 9342-1 



Total per side is 10 with a 
maximum of 5 large per side 



1 TO 10 I/O UNITS OR 
SUBSYSTEMS REQ. LARGE 
PERIPH. CONTLS. 



MODEL 
B 6340 



APPROP. 

TAPE 

P.C. 



CARD 
PUNCH 



MODEL 
B6210 



MODEL 
B6373 



2 X 10EXCH 




DISK 
FILE 
SUB- 
SYSTEM 



Figure 10-1. Input/Output Subsystem 



10-1 



Either processor can initiate an operation on either multiplexor, 
in a two processor/ two multiplexor configuration, by executing a 
Scan In/Out instruction. This instruction transfers an address 
Word and a Data Word to the multiplexor. If the address Word spe- 
cifies an Initiate I/O operation, then the data word is an Area 
Descriptor. The multiplexor fetches the I/O Control Word located 
at the Area Base Address (from the Area Descriptor) and initiates 
the peripheral operation. Upon completion, the I/O Finish Interrupt 
is set. The Result Descriptor is returned when processor executes 
a Read Result Descriptor command. 

DESCRIPTOR FORMATS. 

The formats of the Address Word, Area Descriptor, and I/O Control 

Word, respectively, are illustrated in figure 10-2,. 



47 











































UN 
NO 


It 


F 


Z 



























44 












20 


16 


12 


8 



4 


M 




ADDRESS WORD 







c 








19 














H 
A 




BUFFER | 
LENGTH 




ARE 
BAS 
AD( 


A 
F 










R " 
S 




WC 


RDS 






3RESS 


















20 














AREA DESCRIPTOR 





43 


39 


35 










































45 
























44 


40 


36 


32 




















I/O CONTROL WORD 



Figure 10-2. I/O Descriptor Formats 



10-2 



ADDRESS WORD. 

When M of the address word equals 0, all active multiplexors re- 
spond to the descriptor. When M equals 1, the multiplexor spe- 
cified by the Z field responds to the command. (The 2— bit Z field 
designates a specific multiplexor.) When Z equals 01 and M is 1, 
multiplexor A is selected. When Z equals 10 and M is 1, multiplexor 
B is selected. All other bit combinations in the Z field are not 
used. F-field codes are listed in table 10-1. 



AREA DESCRIPTOR. 

The area base address specifies the base address of the memory area 

Buffer length indicates the size of the area. The first word 

of the area is the I/O Control Word. 

I/O CONTROL WORD. 

The I/O Control Word contains a standard control field and a unit 
control field. Bits 35 - 0, the unit control field, are unique 
for each peripheral control. Bits 45 - 36, the standard control 
field, are defined as follows: 



Bit 



^5 
44 

h3 
42 
41 
40 

39 
38 

37 
36 



Assignment 



Bit = 



Attention 

Read/Write 

Memory Inhibit 

Translate In Unit 

Frame Length 

Memory Protect 

Backward 

Test 

1001 (Tag bit 

0101 field) 

— — — — — Store double-precision 
—— — — Store single-precision 

■ Store program tags. 
———Tag field transfer. 



No 


Yes 


Write 


Read 


No 


Yes 


No 


Yes 


6-bit 


8-bit 


No 


Yes 


No 


Yes 


No 


Yes 



Bit = 1 



10-3 



Table 10-1 
F Field Codes 



» 

Scan 
Oper. 


F Bits 
8765 


Mnem. 


Multiplexor 
Operation 


OUT 


0000 

0011 
0100 

0000 


IOIL 

STOD 
SSIM 

HOP 


Designated MPX to Initiate an i/O Operation. 
Bits 16 through 9 contain Unit Designate. 

Set the Time Of Day Register. 

Set the Interrupt Mask Register. 

Interrogate i/O path for upcoming Initiate 
i/O operation. 


IN 


0001 

0010 
0011 
0100 

0110 

1111 


IPST 

RTOD 

SRIR 
SRIM 

I PUT 

SRIL 


Interrogate Peripheral Status of the desig- 
nated Status Vector. 

Read Result Descriptor. 

Read Time of Day Register. 

Read Interrupt Register or Interrupt Mask 
Register. 

Interrogate Peripheral Unit Type. 

Read Interrupt Literal. 



RESULT DESCRIPTOR. 

The format of the Result Descriptor is shown in figure 10-3. 

Bits 47:20 indicate the final memory address at which the i/O 
operation terminated. Bits 16:17 the error field, is subdivided 
into a standard error field and a unit error field. The unit 
error field bit assignments, bits 15:9 are unique for each peri- 
pheral control. The standard error field bit assignments, bits 
6:7 and 16 are as follows: 



10-4 



Bit 



Assignment 



16 
6 

5 
k 

3 
2 
1 




Memory Protection Error 

Memory Parity Error 

Memory Address Error 

Descriptor Error 

Not Ready 

Busy 

Attention 

Exception 













CHAF 
C 
















M 


!MO 


RY 




O 
U 


UNIT 
NO. 




ERROR 






At 


)DRE 


SS 




N 
T 








FIELD 




44 








28 


24 




16 












Figure 10-3. Result Descriptor Format 

PERIPHERAL UNITS AND ASSOCIATED PERIPHERAL CONTROLS. 
Up to 256 I/O devices may be attached to a 2 multiplexor system. 
These devices communicate with the multiplexor through a maximum 
of 20 peripheral controls. One peripheral control cabinet houses 
10 controls, 5 large and 5 small. Table 10-2 lists the peripheral 
controls available excluding magnetic tape and disk file which are 
listed separately. 

CONSOLE. 

The Console Control Center (figure 10-4) includes the Supervisory 
Display and Keyboard, which allows the operator to communicate with 
the system. The B 63^0 Single Line Control connects the Console 
Control Center and the multiplexor. Up to eight units can be ser- 
viced by one Single line control. Figures 10-5 and 10-6 depict the 
I/O Control word and the result descriptor for the Single Line 
Control . 



10-5 



Style Peripheral Units 


PC 

Style 


PC 

Type 


Peripheral Controls 


B 91 1 1 800 CPM Card Reader 
B 9 1 1 2 1 400 CPM Card Reader 


B 6110 
B 6110 


Small 
Small 


Card Reader Control 
Card Reader Control 


B 9120 500-1000 CPS Paper Tape Reader 


B 6120 


Small 


Paper Tape Reader Control 


B9213 300 CPM Punch 


B 6210 


Small 


Card Punch Control 


B 9220 100 CPS Paper Tape Punch 


B 6220 


Small 


Paper Tape Punch Control 


B 9242-1 860 LPM Printer ( 1 20 Prt. Pos.) 

B 9243-1 1 100 LPM Printer(120 Prt.Pos.,44 Ch.) 


B 6240 
B 6240 


Small 
Small 


Line Printer Control 
Line Printer Control 


B 9342-1 Console Display Terminal 
B 9342-2 Optional Printer/Keyboard 


B 6340 


Large 


Console Display & Optional 
Printer 



Table 10-2. Peripherals and Controls 




Figure 10-4. Console Control Center 



47 










27 






15 


11 


7 




















14 


10 


6 














25 




17 


13 


9 














28 


24 




16 


12 










6:7 Standard Error Field 

7 Memory Access Error 

7 & 9 Information Parity Error 

10 Control Message 

11 No ETX 

12 Unit ID - B9342-1 



10-6 



15 Time Out 

16 Memory Protect Error (Read Only) 
2k r8 Unit Designate 

27:3 Char. Count 

47:20 Memory Address 

Figure 10-5 . Single Line Control Result Descriptor 





43 


39 






















42 


38 






















41 


37 




















44 


40 


36 





















45 


= ATTENTION 




44 


= 1 READ 


4o = 




= WRITE 


39 = 


h3 


= 


38 = 


42 


= 


37 = 


4l 


=18 bit 


36 = 



tag bit field 



Figure 10-6. Single Line Control I/O Control Word 

CARD READER. 

The B 6110 Card Reader Control can be used with either the B 91H 
(800 cpm) or B 9112 (l400 cpm) card readers (figure 10-7). The 
input hopper and the output stacker have a capacity of 2400 cards 
each. The card readers accept alpha, binary or EBCDIC card codes, 
Alpha card code is converted to BCL by the card reader, which is 
then converted into internal BCL or EBCDIC by translators in the 
multiplexor. EBCDIC card code is converted to internal EBCDIC by 
the card reader control (B 6110) . When reading binary punched 
cards no translation is made. 



10-7 



The card readers can read 51? 60, or 80 column punched cards. 
Optional features include the ability to read kO column Treasury 
checks and round holes in Postal Money Orders. Cards of varying 
thickness are acceptable; however, card thickness and length must 
be consistent during any one run. Figures 10-8 and 10-9 depict 
the I/O control word and the result descriptor for card reader 
operations . 




Figure 10-7. Card Reader 





























42 
























41 


37 




















44 


40 


36 





















Figure 10-8. Card Read I/O Control Word 



10-8 



44 = l 




40 = 1 


Memory protect 


39 = 




38 = 




Alpha 




42 = 1 




41 = 


6 bit 


41 = 1 


8 bit 


Binary 




42 = 




41 = 




37 = 




Fl 


gure 10-8. Car 



EBCDIC 
42 = 
41 = 1 



37 tag bit 
36 field 



Card Read i/O Control Word (cont) 



47 










27 










7 






















10 


6 














25 




17 




9 














28 


24 




16 




8 








6:7 Standard Error Field 

7 Memory Access Error 

8 Read Check 

7 & 9 Validity Error 

10 Control card (alpha only) 

16 Memory Protect Error 

24:8 Unit Designate 

27:3 Character Count 

47:20 Memory Address 

Figure 10-9. Card Read Result Descriptor 



10-9 



CARD PUNCH. 

The B 6210 Card Punch Control is used with the B 9-213 Card Punch 
(figure 10-10), which can punch either binary, alpha, or EBCDIC 
code at a rate of 300 cards per minute. Pre-punched cards may be 
used, but previously punched columns cannot be repunched. The 
card punch has a 1000 card capacity input hopper and three output 
stackers (primary, auxiliary and error) which have a capacity of 
1200 cards each. Stacker selection is accomplished programmatically , 
Figures 10-11 and 10-12 depict the I/O control word and the result 
descriptor for the card punch operation. 




Figure 10-10. Card Punch 



10-10 





























42 


38 






















41 


37 




















44 




36 


32 



















44 = 37 "tag bit 

38 = 36 = field 

32 = 1 Auxiliary stacker 

Alpha 

42 = 1 

41 = 6 bit 

41 = 1 8 bit 

Binary 

42 = 

41 = 

37 = 

EBCDIC 

42 = 

41 = 1 

Figure 10-11. Card Punch l/O Control Word 



47 










27 










7 






















10 


6 














25 




17 


















28 


24 
















Figure 10-12. Card Punch Result Descriptor 



10-11 



6:7 Standard Error Field 

7 Punch Check 

7 & 10 Memory Access Error 

24:8 Unit Designate 

21:3 Character Count 

41:20 Memory Address 

Figure 10-12. Card Punch Descriptor (cont) 

LINE PRINTERS. 

Two line printers (figure 10-13) are available foir use on the 

B 65OO system. The B 9242 prints 860 lines per minute (LPM) and 

the B 92^3, 1100 LPM. Both printers are available with either 

120 or 132 print positions. Both have vertical skipping and end- 

of-page formatting controlled by a punched paper tape. The B 6240 

Line Printer Control connects the printer to the multiplexor. 

Translators in the multiplexor convert internal BCL or EBCDIC into 

BCL for transmission to the printer control. Figures 10-14 and 

10-15 show the Printer 1/0 control word and result descriptor. 




Figure 10- 13. Line Printer 



10-12 





43 




35 


31 


















42 


38 


34 


30 


















41 


37 


33 


















44 




36 


32 



















kk = o 

k3 = 

43 = 1 

k2 = 1 

i+1 = 

38 = 

37 

36 = 

35:5 
31 = 1 
30 = 1 



Print 

Space - Inhibit Data Transfer 

Translate to BCL 

6 bit; 41 = 1 8 bit 




Skip to Channel 1 =) 11 
Double Space (only if 35:5 
Single Space ) equals zero 

Figure 10-14. Line Printer I/O Control Word 



47 










27 










7 
























6 














25 




17 




9 














28 


24 






12 


8 








Figure 10-15 . Line Printer Result Descriptor 



10-13 



6:7 Standard Error Field 

8:2 Bit Transfer Error 

9:3 Print Check 

24:8 Unit Designate 

27:3 Character Count 

47; 20 Memory Address 

Figure 10-15 . Line Printer Result Descriptor (cont) 

MAGNETIC TAPE SUBSYSTEM. 

A magnetic tape subsystem can include from one to four tape controls 
servicing from one to sixteen magnetic tape units. Within a single 
tape system all tape units must be used at the same speed and all 
controls must be of the same type. 

A magnetic tape exchange is required when more than one control or 
more than six magnetic tape units are used. 

The number of magnetic tape units on a system is limited only by 
the number of exchanges and peripheral controls employed. The user 
may choose either 7-channel tape or 9-channel tape which may be 
intermixed, provided this is not attempted on the same subsystem. 
The user may also select any of four packing densities up to 1600 
bits per inch and transfer rates from 9,000 to 240,000 bytes per 
second. 

A choice of physical construction may be made between two free 
standing devices which house one tape unit per cabinet (figure 10- 
16), or the cluster unit (figure 10-17) which houses up to four 
tape units per cabinet. The magnetic tape units are capable of 
reading and spacing in either a forward or reverse direction. 
Table 10-3 lists the available magnetic tape subsystems. Figure 
10-18 shows possible configurations of these subsystems. 



10-14 





72KB MTU 



144/1 9 2/2 40KB MTU 



Figure 10-16. Free Standing Magnetic Tape Unit 




Figure 10-17 . Cluster Tape Unit 



10-15 



Table 10-3 
Available Magnetic Tape Subsystems 







Appropriate 








Peripheral 






Description of Magnetic 


Control 


Exchanges 












Style 


Tape Subsystems 


Style 


Quantity 


Style 


Type 


Function 


B 9381-2,3,4 


9 channel 


B 6381-1 


1 


None 


None 


1 Tape 


36KB Cluster 


800/200* BPI, 45 IPS, 










Operation 




2 to 8 Tape Stations 


B 6381-1 


1 or 2 


B 6481 


2x8 


2 Tape 














Operation 


B 9382-2,3,4 


9 channel 


B 6381-2 


1 


None 


None 


1 Tape 


72KB Cluster 


1600 BPI, 45 IPS, 










Operation 




2 to 8 Tape Stations 


B 6381-2 


1 or 2 


B 6481 


2x8 


2 Tape 
Operation 


B 9380-2,3,4 


7 channel 


B 6381-3 


1 


None 


None 


1 Tape 


36KC Cluster 


200/556/800 BPI, 45 IPS, 










Operation 




2 to 8 Tape Stations 


B 6381-3 


1 or 2 


B 6480 


2x8 


2 Tape 
Operation 


B 9391 72 KC 


Either 1 to 6, 1 to 10, or 


B 6391-3 


1 


None 


None 


1 Tape 


Free Stand'g 


1 to 16 Tape Units, 7 Channel, 










Operation 


Tape Unit 


200, 556, and 800 BPI, 
90 IPS 


B 6391-3 


1 or 2 


B 6490 


2x10 


2 Tape 
Operation 






B 6391-3 


1 to 4 


B 6492 


4x16 


4 Tape 
Operation 


B 9392 72KB 


Either 1 to 6, 1 to 10 or 1 to 


B 6393-1 


1 


None 


None 


1 Tape 


Free Stand'g 


16 Tape Units, 9 channel, 










Operation 


Tape Unit 


800/200* BPI, 90 IPS 


B 6393-1 


1 or 2 


B 6490 


2x10 


2 Tape 
Operation 






B 6393-1 


1 to 4 


B 6492 


4x16 


4 Tape 
Operation 


B 9394-1 


Either 1 to 6, or 1 to 10 Tape 


B 6391-4 


1 


None 


None 


1 Tape 


24, 66, or 


Units, 7 channel, 200, 556 or 










Operation 


96KC 


800 BPI, 120 IPS 


B 6391-4 


1 or 2 


B 6490 


2x10 


2 Tape 


Free Stand'g 












Operation 


Tape Unit 














B 9394-2 
96 KB 
Free Stand'g 


Either 1 to 6, 1 to 10 or 1 to 
16 Tape Units, 9 channel, 
800/200* BPI, 120 IPS 


B 6393-3 
B 6393-3 


1 
1 or 2 


None 
B 6490 


None 
2x10 


1 Tape 
Operation 

2 Tape 


Tape Unit 












Operation 






B 6393-3 


1 to 4 


B 6492 


4x16 


4 Tape 
Operation 


B 9393-1 


1 to 8 Tape Units 


B 6393-2 


1 


B 6493-1 


1x8 


1 Tape 


144KB 


9 channel 










Operation 


Free Stand'g 


Phase Encoded 










2 Tape 


Tape Unit 


1600 BPI, 90 IPS 


B 6393-2 


1 or 2 


B 6493-2 


2x8 


Operation 


B 9393-2 


1 to 8 Tape Units 


B 6393-2 


1 


B 6493-1 


1x8 


1 Tape 


192KB 


9 channel 










Operation 


Free Stand'g 


Phase Encoded 










2 Tape 


Tape Unit 


1600 BPI, 120 IPS 


B 6393-2 


1 or 2 


B 6493-2 


2x8 


Operation 


B 9393-3 


1 to 8 Tape Units 


B 6393-2 


1 


B 6493-1 


1x8 


1 Tape 


240KB 


9 channel 










Operation 


Free Stand'g 


Phase Encoded 










2 Tape 


Tape Unit 


1600 BPI, 150 IPS 


B 6393-2 


1 or 2 


B 6493-2 


2x8 


Operation 



A Model B 6681 (for Clusters) or B 6691 or B 6692 (for Free 
be attached to each peripheral control on a 9 channel 800 BPI 



Standing Units) Optional Adapt er must 
tape system to provide 200 BPI capability. 



10-16 



URGE PERIPHERAL CONTROLS 



1/0 

MULTI- 
PLEXOR 




APPROP. 

TAPE 

P.C. 



APPROP. 

TAPE 

P.C. 



Only 10 tope P.C.'s per 1/0 Multiplexor. 

The Uth shown here is for illustration purposes only. 



LARGE PERIPHERAL CONTROLS 



Figure 10-18. Magnetic Tape Configuration 

Figure 10-19 shows the B 65OO magnetic tape I/O control word. This 
word is used to depict the various types of* magnetic tape operations 
possible that are listed in table 10-4. When an operation is 
finished the result descriptor returned is shown in figure 10-20. 



10-17 



OPERATION 


44 


43 


STANDARD CONTROL FIELD 
42 41 40 39 38 


37 


36 


READ BCL 


1 





1 O O O 


O 


O 


READ BINARY 


1 





O O 


O 


O 


READ EBCDIC 


1 





1 O O 


O 


O 


SPACE 


11 


WRITE BCL 








1 O 


O 




WRITE BINARY 











O 




WRITE EBCDIC 








1 


o 




ERASE 





1 


O O 


o 




WRITE TM 















REWIND 





1 


1 






TEST 


1 







BIT 35 = AND 34 = 1 



Table 10-4. Magnetic Tape Operations 





43 


39 


35 


31 


27 


23 














42 


38 


34 


30 


26 
















41 


37 


33 


29 
















44 


40 


36 


32 


28 






16 











44 = 1 Tape Read 

= Tape Write 

43 = 1 Memory Inhibit 

42 = 1 Translate 

41 = 6 bit; =18 bit 

40 = 1 Memory Protect 

39 = Forward; = 1 Backward 
38 = 

37:2 Tag bit field 

35:2 Equal to zero 



Figure 10-19. I/O Control Word Magnetic Tap< 



10-li 



33:^ 



Format 

1000 800 BPI 

1010 555 BPI ( 7 track only) 
1100 200 BPL 

1111 1600 BPI (9 track only) 
0000 Unit selected density 
30 = even parity 
= 1 odd parity 



9 Track Read only 

29 = 1 CRC Correction 

28:2 If 29 = 1 then track to be corrected. 

Space Only 

23:8 decimal value of number of records to be 
spaced, 100 max. 

Figure 10-19. 1/0 Control Word Magnetic Tape (cont) 



47 










27 






15 


11 


7 




















14 


10 


6 














25 




17 


13 


9 














28 


24 




16 


12 


8 








6:7 Standard Error Field 

7 Memory Access Error 

8 End of tape or beginning of tape 

9 Read - end of file; write - lock out 

10 Incomplete Record 

11 Oversized Record 



Figure 10-20. Magnetic Tape Result Descriptor 



10-19 



11:2 Density (test only) 

00 - 800 BPI 

01 - 200 BPI 

10 - 555 BPI 

11 - BPI 

7 & 10 & 11 Mag tape parity error 

12 CRC correction possible, bits 15 ' 3 defines track 

13 Non-present option 

15 6 ft. blank tape 

16 Memory Protect Error (read only) 
24:8 Unit Designate 

27:3 Character Counter 
47:20 Memory Address 

Figure 10-20. Magnetic Tape Result Descriptor (cont) 

DISK FILE SUBSYSTEM. 

The Disk File Subsystem is an extremely high-speed, modular, ran- 
dom information storage system. A basic system consists of one 
electronics unit and from one to five storage units, see figure 
10-21. If more than one basic subsystem is used then an exchange 
may be installed to connect the two subsystems to a disk file 
control. Figure 10-22 shows various disk file configurations al- 
lowed on a B 65OO system. The exchanges involved are located 
within the auxiliary cabinets that are attached to the peripheral 
control cabinets. Each of the disk file controls tire the large 
size controls, therefore, they must be located only in positions 
zero through four in the PCC. 

The various types of disk file subsystems and their capacities 
and speeds are indicated in table 10-5. Figures 10-23 and 10-24 
indicate the disk file I/O control word and the disk file result 
descriptor. 



10-20 



it 



ELECTRONICS UNIT 



STORAGE MODULES 



Figure 10-21. Basic Disk File Subsystem 



PERIPHERAL CONTROLS 
LARGE 



1/0 

MULTI- 
PLEXOR 






MODEL 
B6373 








MODEL 
B 6373 




MODEL 
B 6373 










MODEL 
B 6373 


MODEL 
B 6373 


MODEL 
B6373 


MODEL 
B6373 




MODEL 
B6373 














DISK FILE 
P.C. 


P.C. 


DISK FILE 
P.C. 


DISK FILE 
P.C. 


P.C. 


DISK FILE 
P.C. 


DISK FILE 
P.C. 


DISK FILE 
P.C. 


DISK FILE 
P.C. 


DISK FILE 
P.C. 






































2 X 10EXCH. 




N. x N„ EXCHANGE 






















































1 TO 10 
ELECTRONICS UNITS 




1 TO 20 ELECTRONICS UNIT 








1 TO 5 

DISK MODULES PER 

ELECTRONICS UNIT 


1 TO 5 

DISK MODULES 

PER 

ELECTRONICS UNIT 


















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PERIPHERAL CONTROLS 
LARGE 



Figure 10-22. Disk File Configurations 



10-21 



Table 10-5 
Disk File Subsystem Types 



Disk 


■ 
Electronic 
Unit 


Exchange 


Peripheral 
Control 


Style 


Description 


Style 


Style 


Type 


Function 


Style 


Quantity 


B 9372-11 


10.87 mill, bytes or 
14.5 mill. char. - 20 ms 


B 9371-7 


B 6471 


N lX N 2 


4x20 with 
Appropriate 
Adapters & 
Extension* 


B 6373 
B 7373 




1 to 4 

1 


B 9375-10 


Data Memory Bank 

133 mill. char, or 

100 mill, bytes — 23 ms 


** 
B 9371-8 


B 9376-10 


Addt'l 26.6 mill. char, 
or 20 mill, byte Incre- 
ments - 23 ms 


** 
B 9371-8 


B 9375-12 


Data Memory Bank 
133 mill. char, or 

100 mill, bytes- 40 ms 


** 
B 9371-9 


B 9376-12 


Addt'l 30.5 mill. char, 
or 22.8 mill byte Incre- 
ments — 40 ms 


** 
B 9371-9 


B 9375-13 


Data Memory Bank 
133 mill. char, or 
100 mill, bytes-60 ms 


** 
B 9371-10 


B 9376-13 


Addt'l 26.6 mill. char, 
or 20 mill, byte Incre- 
ments — 60 ms 


** 
B 9371-10 



* A B 6471-5 or B 7471-5 Control Adapter (Nj) is required for each control in the subsystem and a 
B 6471-6 or B 7471-6 EU Adapter (N 2 ) is required for each electronic unit in the subsystem. The 
B 6471-7 or B 7471-7 Exchange Extension is required to go above 10 EU adapters on the sub- 
system. 

** Data Memory Banks and Increments include an electronic unit for every 5 disk modules; however 
additional optional EU's may be ordered for more paths to the disk modules, using stated EU style 
numbers. 



10-22 





43 


39 




31 


















42 
























41 


37 




















44 


40 


36 






















44 = 1 

43 = 

44 = 1 
43 = 1 



42 = 
41 = l 
4o = l 
39 = 1 
37 } 

36 J 

31:24 



Disk File READ 



READ CHECK 



kk = ) WRITE 
43 = ) 



Memory Protect 

Maintenance Segment 

Tag Bit 

Field 

Disk File ADDRESS (decimal) 

Figure 10-23. Disk File I/O Control Word 



47 










27 






15 


11 


7 
























6 














25 




17 




9 














28 


24 




16 




8 








Figure 10-24. Disk File Result Descriptor 



10-23 



6:7 Standard Error Field 

7 Memory Access Error 

8 Unit busy 

9 Write lock out 
7 & 9 Disk Read Error 

11 Went not ready 

15 Time out 

16 Memory protect (READ only) 
24:8 Unit Designate 

27:3 Character counter 

47:20 Memory ADDRESS 

Figure 10-24. Disk File Result Descriptor (cont) 

PAPER TAPE. 

The B 9120 Paper Tape Reader, figure 10-25> is capable of* reading 
punched paper tape at a rate of 1000 characters per second and 
metalized mylar tape or fanfold tape at a rate of 500 characters 
per second. Baudot and BCL to EBCDIC code translation is automatic, 
All other codes are read directly into memory and may be translated 
programmatically . The reader can accommodate 5- ? 6-, 7- » °3r 8 
channel tape as selected by the operator. Tape widths of ll/l6, 
7/8, or 1 inch are interchangeable. 

The paper tape punch, see figure 10-26, is capable of punching a 
standard paper tape format in either BCL or Baudot code. The punch 
accommodates 5- > 6- , 7- » ot 8 channel tape at a maximum rate of 
100 characters per second, punching ten characters to the inch. 
Standard tape widths of ll/l6, 7/8, and 1 inch may be used in 
either the oiled paper tape, dry paper tape, metalized mylar tape, 
or laminated mylar tape. 

Each paper tape I/O control, reader or punch, can accommodate only 
one paper tape unit each. The controls are the smsLll size controls 
which can be set into a PCC cabinet as either a right hand or a 
left hand control. 



10-24 







Figure 10-25. B 9120 Paper Tape Reader 



10-25 



"VfmiftffSPf 




,1 



Figure 10-26. B 9220 Paper Tape Punch 

Figure 10-27 indicates the paper tape control word and the various 
paper tape operations possible on the B 6500. Figure 10-28 in- 
dicates the paper tape result descriptor. 



10-26 





43 


39 


35 




















42 


38 


34 






















37 




















44 




36 





















hh = 1 Tape read 

= Tape punch. 
43 = 1 Inhibit data transfer 
42 = 1 Translate 
39 = Forward; = 1 Backward 
38 = 1 Test 

37:2 Tag field bits 
35 & 36 Formats: 

10 - 8 bit no parity 

00-7 bit info plus 1 parity 

01-6 bit info plus 1 parity 





44 


43 


42 


41 


40 


39 


38 


37 


36 


35 


34 


READ BCL 


1 





1 


O 


O 








O 


O 





1 


READ BINARY 


? 








O 


O 








O 


O 








WRITE BCL 








1 


O 


O 








O 






O 


1 
O 


WRITE BINARY 











O 


O 








O 





PUNCH LEADER 





1 




O 


O 








O 









FWD SPACE 


1 


1 




O 



















BKWD SPACE 


1 


1 




O 




1 














1 REWIND 





1 








1 














Figure 10-27. Paper Tape i/O Control Word and Operations 



10-27 



47 










27 










7 






















10 


6 














25 




17 




9 














28 


24 




16 




8 








6:7 

7 



7 & 9 
10 
16 



Standard Error Field 
Memory Access Error 
Read - EOT or BOT 
Punch - Low Tape 
Read - tape parity error 
Incomplete record 
Memory protect error 



Figure 10-28. Paper Tape Result Descriptor 



10-28 



SECTION 11 
B 6500 DATA COMMUNICATIONS SYSTEM 



GENERAL. 



The B 6500 Data Communications System is comprised of one or- more 
of each of the following units: 

a. Data Communications Processor (D.C.P.). 

Each B 6500 Peripheral Control Multiplexor accommodates 
up to k D.C.P. ! s through the word interfaces. The word 
interfaces provide access to the B 6500 main memory. 

b. Adapter Cluster. 

One Adapter Cluster services up to 16 Line Adapters 
which may have dissimilar characteristics. A maximum 
of 16 Adapter Clusters may be connected to one Data Com- 
munications Processor. It is also possible to connect 
an Adapter Cluster between two Data Communications Pro- 
cessors. This allows the Adapter Cluster to be serviced 
from either D.C.P. 

c. Line Adapter. 

Each communication line requires at least one Line Adap- 
ter. With some types of terminals two Line Adapters may 
be required. Up to 16 Line Adapters are accommodated by 
one Adapter Cluster. 

The B 65OO Data Communications System can service a maximum of 2048 
communications lines. A typical system configuration is shown in 
figure 11-1. 

DATA COMMUNICATIONS PROCESSOR (D.C.P.). 

The Data Communications Processor (D.C.P.) is a special purpose 
processor. It handles the transmitting and receiving of messages 
over the many data communications lines. A part of that task is 
answering calls , terminating calls , observing the formal line dis- 
ciplines, polling operations and the formatting of messages. 



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11-2 



The Data Communications Processor is a stored program computer 
obtaining its program instructions either from B 65OO main mem- 
ory or from an optional local memory. Through the use of the local 
memory the throughput of the D.C.P. is significantly increased due 
to the reduction in instruction fetch time. 

If the optional local memory is not present , the Data Communications 
Processor shares the B 65OO system main memory with the other units 
of the B 65OO. The memory allocation for the D.C.P. is controlled 
by the B 6500 Master Control Program. Data exchanges occur 
when the B 65OO processor initiates a D.C.P. operation and 
when the D.C.P. finishes an operation, i.e. i/O complete signal 
from the D.C.P. 

The internal form of the Data Communications Processor is shown in 
figure 11-2. The Data Communications Processor is an elementary 
micro-programed processor. Two-address and three-address instruc- 
tions, operating on 8-bit bytes, are used by the Data Communications 
Processor. The byte organization fits into a basic half-word 
(three byte) structure permitting efficient half-word transfers 
within the Data Communications Processor. The functions of the 
D.C.P. are accomplished with a small array of intercommunicating 
registers , a simple arithmetic-logical unit and an eight word 
scratchpad memory. 

For complete information on all Data Communications Processor reg- 
isters and memories , refer to the Data Communications Processor 
Reference Manual. 

ADAPTER CLUSTER. 



The Adapter Cluster is the interface between the Data Communications 
Processor and the data-communication Line Adapters. Each Adapter 
Cluster services up to 16 Line Adapters. Data transmission rates 
of from k5.5 B.P.S. to 4800 B.P.S. are handled by the Adapter Clus- 
ter simultaneously. 



11-3 




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Figure 11-3 shows a block diagram of the Adapter Cluster. The 
Adapter Cluster basic functions are: 

a. Line termination: Scanning, clocking and temporary stor- 
age . 

b. Character assembly and disassembly. 

c. Synchronization attainment and maintenance. 

d. Timer operation to maintain line discipline. 

e. Some character recognition logic. (Mainly synchronization 
characters for the various line disciplines). 

f . Provide the ability to exchange information with one or 
two Data Communications Processors. 

The Adapter Cluster functions in a manner that makes it appear 
transparent to most characters and message formats. However as 
stated in item (e) above it does recognize the SYN characters in 
order to attain and retain synchronization when operating in the 
synchronous mode. 

LINE ADAPTER. 



The Line Adapter types that are provided allow the Data Communica- 
tions Processor to interface with data sets, Voice Response Systems 
and the direct connection to remote devices. Each Line Adapter 
terminates one line. The Line Adapter handles the exchange of 
bits or characters between the Adapter Cluster and the data com- 
munication line. The buffer of each type of Line Adapter contains 
either one bit or one character, depending on the type. Table 11-1 
shows a table of terminal compatibility. 

For more detailed information on all phases of the Data Communica- 
tions Processor refer to the Data Communications Processor Refer- 
ence Manual. 



11-5 



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X 



X 



X 













p 












•H 












S 












P 


o 










&n 


o 










S 


*n 










•H 
H 


pq 


o 




o 




H 


^\ 


o 




CM 




cd 


o 


>n 




H 




O 


-* 


en 










en 






H 




o 




pq 




H 


o 


•H 


pq 


\ 







en 


P 


^\ 


o 


o 


I 


o 


erf 


o 


o 


o 


H 


S 


o 


K^ 


in 


CD 




o 


en 


CM 


K\ 


fl 


S 


p 








o 


pq 


3 


ft 


PQ 


pq 


M 


H 


<! 



11-8 



APPENDIX A 
OPEPvATORS , ALPHABETICAL LIST 



NAME MNEMONIC 

ADD ADD 

BIT RESET BRST 

BIT SET BSET 

BRANCH FALSE BRFL 

BRANCH TRUE BRTR 

BRANCH UNCONDITIONAL BRUN 

CHANGE SIGN BIT CHSN 

COMPARE CHARACTERS EQUAL DESTRUCTIVE CEQD 

COMPARE CHARACTERS EQUAL, UPDATE CEQU 

COMPARE CHARACTERS GREATER OR EQUAL, 

DESTRUCTIVE CGED 

COMPARE CHARACTERS GREATER OR EQUAL, 

UPDATE CGEU 

COMPARE CHARACTERS GREATER, DESTRUCTIVE CGTD 



COMPARE CHARACTERS GREATER, UPDATE 

COMPARE CHARACTERS LESS OR EQUAL, 
DESTRUCTIVE 

COMPARE CHARACTERS LESS OR EQUAL, 
UPDATE 

COMPARE CHARACTERS LESS , DESTRUCTIVE 



CGTU 

CLED 

CLEU 
CLSD 



HEXADECIMAL 
CODE 

80 

9E 

96 

AO 

Al 

A2 

8E 

Fk 

FC 

Fl 

F9 
F2 

FA 

F3 

FB 
FO 



A-l 



APPENDIX A (cont ) 
OPERATORS , ALPHABETICAL LIST 



NAME 



MNEMONIC 



HEXADECIMAL 
CODE 



COMPARE CHARACTERS LESS , UPDATE 



CLSU 



F8 



COMPARE CHARACTERS NOT EQUAL, 
DESTRUCTIVE 

COMPARE CHARACTERS NOT EQUAL, 
UPDATE 

CONDITIONAL HALT (all modes) 

COUNT BINARY ONES 

DELETE TOP OF STACK 

DISABLE EXTERNAL INTERRUPT 

DIVIDE 

DUPLICATE TOP OF STACK 

DYNAMIC BIT RESET 

DYNAMIC BIT SET 

DYNAMIC BRANCH FALSE 

DYNAMIC BRANCH TRUE 

DYNAMIC BRANCH UNCONDITIONAL 

DYNAMIC FIELD INSERT 

DYNAMIC FIELD ISOLATE 

DYNAMIC FIELD TRANSFER 

DYNAMIC SCALE LEFT 
A-2 



CNED 



F5 



CNEU 


FD 


HALT 


DF 


CBON 


95 BB 


DLET 


B5 


DEXI 


95 hi 


DIV 


83 


DUPL 


B7 


DBRS 


9F 


DBST 


97 


DBFL 


A8 


DBTR 


A9 


DBUN 


AA 


DINS 


9D 


DISO 


9B 


DFTR 


99 


DSLF 


Cl 



APPENDIX A (cont) 
OPERATORS, ALPHABETICAL LIST 



NAME 

DYNAMIC SCALE RIGHT PINAL 

DYNAMIC SCALE RIGHT ROUND 

DYNAMIC SCALE RIGHT SAVE 

DYNAMIC SCALE RIGHT TRUNCATE 

ENABLE EXTERNAL INTERRUPTS 

END EDIT (edit mode) 

END FLOAT (edit mode) 

ENTER 

EQUAL 

ESCAPE TO 16 -BIT INSTRUCTION 

EVALUATE DESCRIPTOR 

EXCHANGE 

EXECUTE SINGLE MICRO, SINGLE POINTER 
UPDATE 

EXECUTE SINGLE MICRO, DESTRUCTIVE 

EXECUTE SINGLE MICRO, UPDATE 

EXIT 

EXTENDED MULTIPLY 

FIELD INSERT 
FIELD ISOLATE 





HEXADECIMAL 


MNEMONIC 


CODE 


DSRF 


C7 


DSRR 


C9 


DSRS 


C5 


DSRT 


C3 


EEXI 


95 46 


ENDE 


DE 


ENDF 


D5 


ENTR 


AA 


EQUL 


8C 


VARI 


95 


EVAL 


AC 


EXCH 


B6 



EXPU 

EXSD 

EXSU 

EXIT 

MULX 

INSR 
ISOL 



DD 
D2 
DA 

A3 
8F 

9C 
9A 



A-3 



APPENDIX A (cont) 
OPERATORS , ALPHABETICAL LIST 



NAME 
FIELD TRANSFER 
GREATER THAN 
GREATER THAN OR EQUAL 
IDLE UNTIL INTERRUPT 
INDEX 

INDEX AND LOAD NAME 
INDEX AND LOAD VALUE 
INPUT CONVERT, DESTRUCTIVE 
INPUT CONVERT UPDATE 
INSERT CONDITIONAL (edit mode) 
INSERT DISPLAY SIGN (edit mode) 
INSERT MARK STACK 
INSERT OVERPUNCH (edit mode) 
INSERT UNCONDITIONAL (edit mode) 
INTEGER DIVIDE 
INTEGERIZE, ROUNDED 
INTEGERIZE, TRUNCATED 
INTEGERIZE, ROUNDED DOUBLE-PRECISION 





HEXADECIMAL 


MNEMONIC 


CODE 


FLTR 


98 


GRTR 


8A 


GREQ 


89 


IDLE 


95 hh 


INDX 


A6 


NXLN 


A5 


NXLV 


AD 


ICVD 


CA 


ICVU 


CB 


INSC 


DD 


INSG 


D9 


IMKS 


CF 


INOP 


D8 


INSU 


DC 


IDIV 


9k 


NTGR 


91 


NT I A 


96 


NTGD 


95 91 



A-4 



APPENDIX A (cont) 
OPERATORS , ALPHABETICAL LIST 



NAME 



INTERRUPT OTHER PROCESSORS 



INVALID OPERATOR (all modes) 



JOIN TWO SINGLES TO DOUBLE 



LEADING ONE TEST 



LINKED LIST LOOKUP 



LESS THAN 



LESS THAN OR EQUAL 



LIT CALL ONE 



LIT CALL ZERO 



LIT CALL 8 BITS 



LIT CALL 16 BITS 



LIT CALL 48 BITS 



LOAD 



LOAD TRANSPARENT 



LOGICAL AND 



LOGICAL EQUAL 



LOGICAL EQUIVALENCE 



LOGICAL NEGATE 



LOGICAL OR 





HEXADECIMAL 


MNEMONIC 


CODE 


HEYU 


95 4F 


NVLD 


FF 


JOIN 


95 42 


L0G2 


95 8B 


LLLU 


95 BD 


LESS 


88 


LSEQ 


8B 


ONE 


Bl 


ZERO 


BO 


LT8 


B2 


LT16 


B3 


LT48 


BE 


LOAD 


BD 


LODT 


95 BC 


LAND 


90 


SAME 


9k 


LEQV 


93 


LNOT 


92 


LOR 


91 



A-5 



APPENDIX A (cont) 
OPERATORS , ALPHABETICAL LIST 



NAME 



MAKE PROGRAM CONTROL WORD 



MARK STACK 



MASKED SEARCH FOR EQUAL 



MOVE CHARACTERS (edit mode) 

MOVE NUMERIC UNCONDITIONAL (edit mode) MVNU 



MOVE TO STACK 



MOVE WITH FLOAT (edit mode) 
MOVE WITH INSERT (edit mode) 



MULTIPLY 



NAME CALL 



NO OPERATION (all modes) 



NOT EQUAL 



OCCURS INDEX 



OVERWRITE DESTRUCTIVE 



OVERWRITE NON -DESTRUCTIVE 



PACK DESTRUCTIVE 



PACK UPDATE 



PUSH DOWN STACK REGISTERS 





HEXADECIMAL 


MNEMONIC 


CODE 


MPCW 


BF 


MKST 


AE 


SRCH 


95 BE 


MCHR 


D7 


) MVNU 


D6 


MVST 


95 AF 


MFLT 


Dl 


MINS 


DO 


MULT 


82 


NAMC 


ko => 7F 


NOOP 


FE 


NEQL 


8D 


OCRX 


95 85 


OVRD 


BA 


OVRN 


BB 


PA CD 


Dl 


PACU 


D9 


PUSH 


Bk 



A-6 



APPENDIX A (cont ) 
OPERATORS , ALPHABETICAL LIST 



NAME 



READ AND CLEAR OVERFLOW FLIP-FLOP 



READ PROCESSOR IDENTIFICATION 



READ PROCESSOR REGISTER 



READ TAG FIELD 



READ TRUE/FALSE FLIP-FLOP 



READ WITH LOCK 



REMAINDER DIVIDE 



RESET FLOAT (edit mode) 



RETURN 



ROTATE STACK DOWN 



ROTATE STACK UP 



SCALE LEFT 



SCALE RIGHT FINAL 



SCALE RIGHT ROUND 



SCALE RIGHT SAVE 



SCALE RIGHT TRUNCATE 



SCAN IN 



SCAN OUT 



SCAN WHILE EQUAL, DESTRUCTIVE 





HEXADECIMAL 


MNEMONIC 


CODE 


ROFF 


D7 


WHOI 


95 ^E 


RPRR 


95 B8 


RTAG 


95 B5 


RTFF 


DE 


RDLK 


95 BA 


RDIV 


85 


RSTF 


D4 


RETN 


A7 


RSDN 


95 B7 


RSUP 


95 B6 


SCLF 


CO 


SCRF 


C6 


SCRR 


C8 


SCRS 


Ck 


SCRT 


C2 


SCNI 


95 ^A 


SCNO 


95 ^B 


SEQD 


95 h¥ 



A-7 



APPENDIX A (cont) 
OPERATORS , ALPHABETICAL LIST 



NAME 

SCAN WHILE EQUAL, UPDATE 

SCAN WHILE FALSE, DESTRUCTIVE 

SCAN WHILE FALSE, UPDATE 

SCAN WHILE GREATER OR EQUAL, 
DESTRUCTIVE 

SCAN WHILE GREATER OR EQUAL, 
UPDATE 

SCAN WHILE GREATER, DESTRUCTIVE 

SCAN WHILE GREATER, UPDATE 

SCAN WHILE LESS OR EQUAL, 
DESTRUCTIVE 

SCAN WHILE LESS OR EQUAL, UPDATE 

SCAN WHILE LESS , DESTRUCTIVE 

SCAN WHILE LESS , UPDATE 

SCAN WHILE NOT EQUAL, DESTRUCTIVE 

SCAN WHILE NOT EQUAL, UPDATE 

SCAN WHILE TRUE, DESTRUCTIVE 

SCAN WHILE TRUE, UPDATE 

SET EXTERNAL SIGN 

SET INTERVAL TIMER 





HEXADECIMAL 


MNEMONIC 


CODE 


SEQU 


95 FC 


SWFD 


95 T)k 


SWFU 


95 DC 



SGED 

SGEU 
SGTD 
SGTU 

SLED 

SLEU 
SLSD 

SLSU 
SNED 

SNEU 
SWTD 
SWTU 
SXSN 
SINT 



95 Fl 

95 F9 

95 F2 
95 FA 

95 F3 
95 FB 
95 FO 
95 F8 
95 F5 
95 FD 
95 B5 
95 DD 
D6 
95 h5 



A-8 



APPENDIX A (cont ) 
OPERATORS , ALPHABETICAL LIST 



NAME 

SET PROCESSOR REGISTER 

SET TAG FIELD 

SET TO DOUBLE-PRECISION 

SET TO SINGLE-PRECISION, ROUNDED 

SET TO SINGLE-PRECISION, 
TRUNCATED 

SKIP FORWARD DESTINATION 
CHARACTERS (edit mode) 

SKIP FORWARD SOURCE CHARACTERS 
(edit mode) 

SKIP REVERSE DESTINATION 
CHARACTERS (edit mode) 

SKIP REVERSE SOURCE CHARACTERS 
(edit mode) 

SPLIT DOUBLE TO TWO SINGLES 

STEP AND BRANCH 

STORE DESTRUCTIVE 

STORE NON -DESTRUCTIVE 

STRING ISOLATE 

STUFF ENVIRONMENT 





HEXADECIMAL 


MNEMONIC 


CODE 


SPRR 


95 B9 


STAG 


95 Bk 


XTND 


CE 


SNGL 


CD 



SNGT 
SFDC 
SFSC 
SRDC 

SRSC 
SPLT 
STBR 
STOD 
STON 
SISO 
STFF 



CC 
DA 
D2 
DB 

D3 

95 ^3 

A4 

B8 

B9 

D5 

AF 



A-9 



APPENDIX A (cont) 
OPERATORS , ALPHABETICAL LIST 



NAME 



SUBTRACT 



MNEMONIC 



SUBT 



TABLE ENTER EDIT , DESTRUCTIVE 

TABLE ENTER EDIT , UPDATE 

TRANSFER UNCONDITIONAL, DESTRUCTIVE 

TRANSFER UNCONDITIONAL, UPDATE 

TRANSFER WHILE EQUAL, DESTRUCTIVE 

TRANSFER WHILE EQUAL, UPDATE 

TRANSFER WHILE GREATER OR EQUAL, 
DESTRUCTIVE 

TRANSFER WHILE GREATER OR EQUAL, 
UPDATE 

TRANSFER WHILE GREATER, DESTRUCTIVE 

TRANSFER WHILE GREATER, UPDATE 

TRANSFER WHILE LESS OR EQUAL, 
DESTRUCTIVE 

TRANSFER WHILE FALSE, DESTRUCTIVE 

TRANSFER WHILE FALSE, UPDATE 

TRANSFER WHILE TRUE, DESTRUCTIVE 

TRANSFER WHILE TRUE, UPDATE 



TEED 
TEEU 
TUND 

TUNU 
TEQD 
TEQU 

TGED 

TGEU 
TGTD 
TGTU 

TLED 
TWFD 
TWFU 
TWTD 
TWTU 



TRANSFER WHILE LESS OR EQUAL, UPDATE TLEU 



HEXADECIMAL 
CODE 

81 

DO 

D8 

E6 

EE 

Eh 

EC 

El 

E9 
E2 
EA 

E3 

95 D2 
95 DA 
95 D3 
95 DB 
EB 



A-10 



APPENDIX A (cont) 
OPERATORS, ALPHABETICAL LIST 



NAME 



TRANSFER WHILE LESS , DESTRUCTIVE 



TRANSFER WHILE LESS , UPDATE 



TRANSFER WHILE NOT EQUAL, DESTRUCTIVE TNED 



TRANSFER WHILE NOT EQUAL, UPDATE 



TRANSFER WORDS OVERWRITE DESTRUCTIVE 



TRANSFER WORDS OVERWRITE UPDATE 



TRANSFER WORDS , DESTRUCTIVE 



TRANSFER WORDS , UPDATE 



TRANSLATE 



UNPACK ABSOLUTE, DESTRUCTIVE 



UNPACK ABSOLUTE, UPDATE 



UNPACK SIGNED, DESTRUCTIVE 



UNPACKED SIGNED , UPDATE 



VALUE CALL 



MNEMONIC 


CODE 


TLSD 


EO 


TLSU 


E8 


5 TNED 


E5 


TNEU 


ED 


TWOD 


Bk 


TWOU 


DC 


TWSD 


D3 


TWSU 


DB 


TRNS 


95 D7 


UABD 


95 Dl 


UABU 


95 D9 


USND 


95 DO 


USNU 


95 D8 


VALC 


00 => 3F 



A-ll 



APPENDIX B 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

DF 

FE 

FF 

00 => 3F 

40 =) 7F 

80 

81 

82 

83 

8k 

85 
86 

87 
88 

89 
8A 
8B 
8C 



NAME 
CONDITIONAL HALT (UNIVERSAL OPERATOR) 
NO OPERATION (UNIVERSAL OPERATOR) 
INVALID OPERATOR (UNIVERSAL OPERATOR) 
VALUE CALL 
NAME CALL 
ADD 

SUBTRACT 
MULTIPLY 
DIVIDE 

INTEGER DIVIDE 

REMAINDER DIVIDE 

INTEGERIZE, TRUNCATED 

INTEGERIZE, ROUNDED 

LESS THAN 

GREATER THAN OR EQUAL 

GREATER THAN 

LESS THAN OR EQUAL 

EQUAL 



MNEMONIC 
HALT 
NOOP 
NVLD 
VALC 
NAMC 
ADD 
SUBT 
MULT 
DIVD 
IDIV 
RDIV 
NT I A 
NTGR 
LESS 
GREQ 
GRTR 
LSEQ 
EQUL 



B-l 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

8D 
8E 
8F 
90 
91 
92 
93 
9h 

95 
96 
91 



NAME 



99 
9A 
9B 
9C 
9D 
9E 



NOT EQUAL 



CHANGE SIGN BIT 



EXTENDED MULTIPLY 



LOGICAL AND 



LOGICAL OR 



LOGICAL NEGATE 



LOGICAL EQUIVALENCE 



LOGICAL EQUAL 



ESCAPE TO 16 -BIT INSTRUCTION 



BIT SET 



DYNAMIC BIT SET 



FIELD TRANSFER 



DYNAMIC FIELD TRANSFER 



FIELD ISOLATE 



DYNAMIC FIELD ISOLATE 



FIELD INSERT 



DYNAMIC FIELD INSERT 



BIT RESET 



MNEMONIC 
NEQL 
CHSN 
MULX 
LAND 
LOR 
LNOT 
LEQV 
SAME 
VARI 
BSET 
DBST 
FLTR 
DFTR 
ISOL 
DISO 
INSR 
DINS 
BRST 



B-; 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

9F 

AO 

Al 

A2 

A3 
Ak 

A5 
A6 

A7 
A8 

A9 
AA 
AB 
AC 
AD 
AE 
AF 
BO 



NAME 



DYNAMIC BIT RESET 



BRANCH FALSE 



BRANCH TRUE 



BRANCH UNCONDITIONAL 



EXIT 



STEP AND BRANCH 



INDEX AND LOAD NAME 



INDEX 



RETURN 



DYNAMIC BRANCH FALSE 



DYNAMIC BRANCH TRUE 



DYNAMIC BRANCH UNCONDITIONAL 



ENTER 



EVALUATE DESCRIPTOR 



INDEX AND LOAD VALUE 



MARK STACK 



STUFF ENVIRONMENT 



LIT CALL ZERO 



MNEMONIC 
DBRS 
BRFL 
BRTR 
BRUN 
EXIT 
STBR 
NXLN 
INDX 
RETN 
DBFL 
DBTR 
DBUN 
ENTR 
EVAL 
NXLV 
MKST 
STFF 
ZERO 



B-3 



APPENDIX B (cont) 



OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

Bl 

B2 

B3 
Bk 

B5 
B6 

B7 
B8 

B9 
BA 
BB 
BD 
BE 
BF 
CO 
CI 
C2 
C3 



NAME 



LIT CALL ONE 



LIT CALL 8 BITS 



LIT CALL 16 BITS 



PUSH DOWN STACK REGISTERS 



DELETE TOP OF STACK 



EXCHANGE 



DUPLICATE TOP OF STACK 



STORE DESTRUCTIVE 



STORE NON-DESTRUCTIVE 



OVERWRITE DESTRUCTIVE 



OVERWRITE NON -DESTRUCTIVE 



LOAD 



LIT CALL 48 BITS 



MAKE PROGRAM CONTROL WORD 



SCALE LEFT 



DYNAMIC SCALE LEFT 



SCALE RIGHT TRUNCATE 



DYNAMIC SCALE RIGHT TRUNCATE 



MNEMONIC 
ONE 
LT8 
LT16 
PUSH 
DLET 
EXCH 
DUPL 
STOD 
STON 
OVRD 
OVRN 
LOAD 
LT48 
MPCW 
SCLF 
DSLF 
SCRT 
DSRT 



B-k 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

Ck 

C5 

C6 

C7 

C8 

C9 
CA 
CB 
CC 
CD 
CE 
CP 
DO 
Dl 
D2 

D3 
D4 

D5 



NAME 



SCALE RIGHT SAVE 



DYNAMIC SCALE RIGHT SAVE 



SCALE RIGHT FINAL 



DYNAMIC SCALE RIGHT FINAL 



SCALE RIGHT ROUND 



DYNAMIC SCALE RIGHT ROUND 



INPUT CONVERT , DESTRUCTIVE 



INPUT CONVERT , UPDATE 



SET TO SINGLE-PRECISION , TRUNCATED 



SET TO SINGLE-PRECISION, ROUNDED 



SET TO DOUBLE-PRECISION 



INSERT MARK STACK 



TABLE ENTER EDIT , DESTRUCTIVE 



PACK DESTRUCTIVE 



EXECUTE SINGLE MICRO , DESTRUCTIVE 



TRANSFER WORDS , DESTRUCTIVE 



TRANSFER WORDS OVERWRITE DESTRUCTIVE 



STRING ISOLATE 



MNEMONIC 
SCRS 
DSRS 
SCRF 
DSRF 
SCRR 
DSRR 
ICVD 
ICVU 
SNGT 
SNGL 
XTND 
IMKS 
TEED 
PACD 
EXSD 
TWSD 
TWOD 
SISO 



B-5 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

D6 

D7 

D8 

D9 
DA 
DB 
DC 
DD 

DE 

EO 
El 

E2 

E3 
E4 

E5 

e6 

E8 
B-6 



NAME MNEMONIC 

SET EXTERNAL SIGN SXSN 

READ AND CLEAR OVERFLOW FLIP-FLOP ROFF 

TABLE ENTER EDIT , UPDATE TEEU 

PACK UPDATE PACU 

EXECUTE SINGLE MICRO , UPDATE EXSU 

TRANSFER WORDS , UPDATE TWSU 

TRANSFER WORDS OVERWRITE UPDATE TWOU 

EXECUTE SINGLE MICRO , SINGLE POINTER EXPU 
UPDATE 

READ TRUE/FALSE FLIP-FLOP RTFF 

TRANSFER WHILE LESS , DESTRUCTIVE TLSD 

TRANSFER WHILE GREATER OR EQUAL, TGED 
DESTRUCTIVE 

TRANSFER WHILE GREATER, DESTRUCTIVE TGTD 

TRANSFER WHILE LESS OR EQUAL, DESTRUCTIVE TLED 



TRANSFER WHILE EQUAL, DESTRUCTIVE 



TRANSFER WHILE NOT EQUAL, DESTRUCTIVE 



TRANSFER UNCONDITIONAL, DESTRUCTIVE 



TRANSFER WHILE LESS , UPDATE 



TEQD 



TNED 



TUND 



TLSU 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

E9 

EA 
EB 
EC 
ED 
EE 
FO 
FL 

F2 
F3 



NAME MNEMONIC 

TRANSFER WHILE GREATER OR EQUAL, 

UPDATE TGEU 

TRANSFER WHILE GREATER, UPDATE TGTU 

TRANSFER WHILE LESS OR EQUAL, UPDATE TLEU 

TRANSFER WHILE EQUAL, UPDATE TEQU 

TRANSFER WHILE NOT EQUAL, UPDATE TNEU 

TRANSFER UNCONDITIONAL, UPDATE TUNU 

COMPARE CHARACTERS LESS , DESTRUCTIVE CLSD 

COMPARE CHARACTERS GREATER OR EQUAL, 

DESTRUCTIVE CGED 

COMPARE CHARACTERS GREATER, DESTRUCTIVE CGTD 



COMPARE CHARACTERS LESS OR EQUAL, 
DESTRUCTIVE 



CLED 



F5 

F8 
F9 

FA 



COMPARE CHARACTERS EQUAL, DESTRUCTIVE CEQD 

COMPARE CHARACTERS NOT EQUAL, 

DESTRUCTIVE CNED 

COMPARE CHARACTERS LESS , UPDATE CLSU 

COMPARE CHARACTERS GREATER OR EQUAL, 

UPDATE CGEU 

COMPARE CHARACTERS GREATER, UPDATE CGTU 



B-7 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



PRIMARY MODE. 

HEXADECIMAL 
CODE 

FB 

FC 

FD 
VARIANT MODE. 
95 ^2 
95 t+3 
95 hh 
95 ^5 
95 h6 
95 hi 
95 hk 
95 ^B 
95 ^E 
95 hT 
95 85 
95 87 
95 8B 



NAME 

COMPARE CHARACTERS LESS OR EQUAL, 
UPDATE 

COMPARE CHARACTERS EQUAL, UPDATE 

COMPARE CHARACTERS NOT EQUAL, UPDATE 



SET TWO SINGLES TO DOUBLE 



SET DOUBLE TO TWO SINGLES 



IDLE UNTIL INTERRUPT 



SET INTERVAL TIMER 



ENABLE EXTERNAL INTERRUPTS 



DISABLE EXTERNAL INTERRUPTS 



SCAN IN 



SCAN OUT 



READ PROCESSOR IDENTIFICATION 



INTERRUPT OTHER PROCESSORS 



OCCURS INDEX 



INTEGERIZE, ROUNDED, DOUBLE-PRECISION 



LEADING ONE TEST 



MNEMONIC 

CLEU 
CEQU 

CNEU 



JOIN 
SPLT 
IDLE 
SINT 
EEXI 
DEXI 
SCNI 
SCNO 
WHOI 
HEYU 
OCRX 
NTGD 
LOG 2 



B-i 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



VARIANT MODE. 



HEXADECIMAL 


CODE 


95 


AF 


95 


B4 


95 


B5 


95 


B6 


95 


B7 


95 


B8 


95 


B9 


95 


BA 


95 


BB 


95 


BC 


95 


BD 


95 


BE 


95 


DO 


95 


Dl 


95 


D2 


95 


D3 


95 


D^ 


95 


D5 



NAME 



MOVE TO STACK 



SET TAG FIELD 



READ TAG FIELD 



ROTATE STACK UP 



ROTATE STACK DOWN 



READ PROCESSOR REGISTER 



SET PROCESSOR REGISTER 



READ WITH LOCK 



COUNT BINARY ONES 



LOAD TRANSPARENT 



LINKED LIST LOOKUP 



MASKED SEARCH FOR EQUAL 



UNPACK SIGNED , DESTRUCTIVE 



UNPACK ABSOLUTE, DESTRUCTIVE 



TRANSFER WHILE FALSE, DESTRUCTIVE 



TRANSFER WHILE TRUE, DESTRUCTIVE 



SCAN WHILE FALSE, DESTRUCTIVE 



SCAN WHILE TRUE, DESTRUCTIVE 



MNEMONIC 
MVST 
STAG 
RTAG 
RSUP 
RSDN 
RPRR 
SPRR 
RDLK 
CBON 
LODT 
LLLU 
SRCH 
USND 
UABD 
TWFD 
TWTD 
SWFD 
SWTD 



B-9 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



VARIANT MODE. 

HEXADECIMAL 
CODE 

95 D7 

95 D8 

95 D9 

95 DA 

95 DB 

95 DC 

95 DD 

95 FO 

95 Fl 

95 F2 
95 F3 
95 F4 
95 F5 
95 F8 
95 F9 
95 FA 
95 FB 



NAME MNEMONIC 

TRANSLATE TRNS 

UNPACK SIGNED, UPDATE USNU 

UNPACK ABSOLUTE, UPDATE UABU 

TRANSFER WHILE FALSE, UPDATE TWFU 

TRANSFER WHILE TRUE , UPDATE TWTU 

SCAN WHILE FALSE, UPDATE SWFU 

SCAN WHILE TRUE , UPDATE SWTU 

SCAN WHILE LESS , DESTRUCTIVE SLSD 

SCAN WHILE GREATER OR EQUAL, 

DESTRUCTIVE SGED 

SCAN WHILE GREATER, DESTRUCTIVE SGTD 

SCAN WHILE LESS OR EQUAL, DESTRUCTIVE SLED 

SCAN WHILE EQUAL, DESTRUCTIVE SEQD 

SCAN WHILE NOT EQUAL, DESTRUCTIVE SNED 

SCAN WHILE LESS , UPDATE SLSU 

SCAN WHILE GREATER OR EQUAL , UPDATE SGEU 

SCAN WHILE GREATER, UPDATE SGTU 

SCAN WHILE LESS OR EQUAL, UPDATE SLEU 



B-10 



APPENDIX B (cont ) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



VARIANT MODE. 

HEXADECIMAL 
CODE 

95 FC 

95 FD 

EDIT MODE. 

DO 

Dl 

D2 

D3 
D4 

D5 
D6 

D7 

D8 

D9 
VARIANT MODE. 
DA 
DB 
DC 



NAME 



SCAN WHILE EQUAL, UPDATE 



SCAN WHILE NOT EQUAL, UPDATE 



MOVE WITH INSERT 



MOVE WITH FLOAT 



SKIP FORWARD SOURCE CHARACTERS 



SKIP REVERSE SOURCE CHARACTERS 



RESET FLOAT 



END FLOAT 



MOVE NUMERIC UNCONDITIONAL 



MOVE CHARACTERS 



INSERT OVERPUNCH 



INSERT DISPLAY SIGN 



SKIP FORWARD DESTINATION CHARACTERS 



SKIP REVERSE DESTINATION CHARACTERS 



MNEMONIC 
SEQU 

SNEU 



MINS 
MFLT 
SFSC 
SRSC 
RSTF 
ENDF 
MVNU 
MCHR 
INOP 
INSG 



INSERT UNCONDITIONAL 



SFDC 



SRDC 



INSU 



B-ll 



APPENDIX B (cont) 
OPERATORS , NUMERICAL LIST PRIMARY MODE 



VARIANT MODE. 



HEXADECIMAL 

CODE NAME MNEMONIC 

DD INSERT CONDITIONAL INSC 

DE END EDIT ENDE 



B-12 



APPENDIX C 
CONTROL WORD FORMATS 





P. 
47 




R. 
43 










39 


35 


31 


27 


23 




19 




15 


11 


7 


3 


1 

50 




C. 
46 





42 




38 


LENGTH/INDEX 
34 30 26 


22 


MEM/DISK ADDRESS 
18 14 10 6 2 





49 




1. 
45 





41 






37 


33 


29 


25 


21 


17 


13 


9 


5 


1 


1 
48 




S. 
44 




D. 
40 




36 


32 


28 


24 


20 


16 


12 


8 


4 






DATA DESCRIPTOR 



P = PRESENCE BIT 


C = COPY BIT 


I 


= INDEX BIT 


S = SEGMENTED 
BIT 


1 = PRESENT IN 


1 = A COPY 


1 


= INDEXED 


1 = AREA 


MAIN MEMORY 








SEGMENTED 


= NOT PRESENT IN 


O = ORIGINAL 


O 


= NON INDEXED 


O = NOT 


MAIN MEMORY 








SEGMENTED 


READ ONLY BIT 


k2 & kl 


D 


= DOUBLE- PRECISION BIT 



1 = READ ONLY 
O = READ/WRITE 



MUST = OO 
FOR DATA DESC 



1 = DOUBLE- PRECISION DATA 
= SINGLE- PRECISION DATA 



50 



49 



48 



47 



46 



ADDRESS COUPLE 
10 6 2 



13 



12 



11 



NORMAL INDIRECT REFERENCE WORD 



C-1 



APPENDIX C (cont) 
CONTROL WORD FORMATS 







47 






43 


39 






35 


31 


27 


23 










11 


7 


3 



50 






1 
46 


42 


38 


DISPLACEMENT 
34 30 26 22 




INDEX FIELD 
10 A ? 



49 






STACK r> 
45 41 


JO. 
37 ! 


33 


29 


25 


21 






9 


5 


1 


1 

48 






44 


40 


36; 


32 


28 


24 


20 






12 


8 


4 






STUFFED INDIRECT REFERENCE WORD 





D.S. 
47 


vi; : ; : ; : ' 




43 


39 


[;•;:•:;•;:; 


35 1 31 


27 


23 




V. 
19 




15 






11 


7 


3 



50 




E. 
46 




STAO 
42 


C NO. 
38 


Dl 
34 


SPLAC 
30 


EMEh 
26 


JT 
22 






LL 
18 14 


10 


6 


2 


1 
49 






45 


41 


37 


33 


29 


25 


21 


h 
:;•:•:::•:::•:::•:•:;:;:;: 




17 






(DF) PREVIOUS " 
13 9 5 


1 


1 
48 


44 


40 


36 


32 


28 


24 


20 






16 


12 


8 


4 






MARK STACK CONTROL WORD 



D.S. = DIFFERENT 
STACK BIT 

1= A N ON- CURRENT 
STACK 

O = THIS CURRENT 
STACK 



E. = ENVIRONMENT 



1 = ACTIVE MSCW 



O = INACTIVE MSCW 



V. = VALUE BIT 



1 = RETURN A VALUE 



O = RESTART FROM BEGIN 





'■ : - ■::':■'■'■'■ 




;■".... 


43 


39 




35 


i 


31 


27 


23 




N. 
19 




15 


Plijl 1 1 


7 


3 


1 

50 


42 


38 


P.S.R- 
34 


F 
30 


U.R. 
26 


22 






L 
18 


L 
14 


iii 10 


6 


2 


1 
49 






ST 
45 


ACK h 
41 


JO. 
37 


33 


29 


25 


21 




17 

16 


r: ' : ' : ' : '' ; ' 


S. D. 
13 9 


NDE> 
5 


1 


1 
48 


U 


40 


36 








32 


28 


24 


20 






12 8 


4 






PROGRAM CONTROL WORD 



C-2 



APPENDIX C (cont) 
CONTROL WORD FORMAT 



N = NORMAL/CONTROL STATE F/F 
1 = CONTROL STATE 
= NORMAL STATE 



SD = Segment Descriptor 





: 


E.S. 
47 








35 




31 


27 


23 


"""In. 


8S8 


15 




11 


7 


3 



50 


O. 

46 


RS.R. 
34 


30 


\I.R 
26 


22 




LL 
18 14 


10 


6 


2 


1 
49 


T. 
45 


33 


29 


25 


21 


17 




13 


S.D. 
9 


NDEX 
5 1 


1 
48 


F. 
44 






32 


28 


24 


20 


16 


12 


8 


4 






RETURN CONTROL WORD 



E.S. = EXTERNAL SIGN 
BIT 
1 = NEGATIVE 
= POSITIVE 



F = FLOAT F/F 

1 = FLOAT 

= NO FLOAT 



= OVERFLOW F/F 

1 = OVERFLOW 

= NO OVERFLOW 



Tr = TRACE MODE 

T = TRUE/FALSE F/F 
1 = TRUE 
= FALSE 

TFOF = TRUE/FALSE F/F 

OCCUPIED F/F 
1 = TFFF VALID 
= TFFF NOT DETERMINED 



N = NORMAL/CONTROL F/F 
1 = CONTROL STATE 
= NORMAL STATE 







47 


43 


39 




35 


31 


27 


23 




j 




15 


11 


7 


3 


1 

50 


INC 
46 


IRE ME 
42 


NT 
38 


F 
34 


INAL 
30 


VALU 
26 


E 
22 


CL 

14 


JRREN 
10 


T VAL 
6 


UE 
2 



49 


45 


41 


37 


33 


29 


25 


21 


13 


9 


5 


1 



48 


44 


40 


36 


32 


28 


24 


20 


12 


8 


4 






STEP INDEX WORD 



C-3 



APPENDIX C (cont) 
CONTROL WORD FORMATS 





P. 
47 


x:-::-:::™ 






R. 
43 






39 


35 


31 


27 


23 




19 


15 


11 


7 


3 


1 

50 




C. 
46 






sz. 

42 




LENGTH IN CHARACTERS 
38 34 30 26 22 


£§£!?■ 


18 


EM/DISK ADDRESS 
14 10 6 2 



49 






i. 

45 


SZ. 

41 


37 


33 


29 


25 


21 




17 


13 


9 


5 


1 


1 
48 


: : : : : : : : :*:* 




s. 

44 


MM 


SZ. 
40 




36 


32 


28 


24 


20 


16 


12 


8 


4 






STRING DESCRIPTOR (NON- INDEXED) 



p 


= PRESENCE BIT 


C = COPY BIT 


I = INDEX BIT 


S 


= SEGMENTED 
BIT 


1 


= PRESENT IN 
MAIN MEMORY 


1 = A COPY 




1 


= STRING 
SEGMENTED 





= NOT PRESENT IN 


O = ORIGINAL 


O = NON- INDEXED 





= NOT 




MAIN MEMORY 








SEGMENTED 


R 


= READ ONLY BIT 


SIZE = k => 8-BIT BYTE 






1 


= READ ONLY 


SIZE = 3 =) 6-BIT CHARACTER 









= READ/ WRITE 


SIZE = 2 => 4-BIT DIGIT 












"B 

Y39 
-T — 
E 
38 

X36 




] 35 


31 


27 


23 










V 
! 34 


VORD 
30 


INDE 
26 


X 
22 






; 33 


29 


25 


21 






1 32 


28 


24 


20 





STRING DESCRIPTOR (INDEXED) 



C-4 



APPENDIX C (cont) 
CONTROL WORD FORMATS 



p 


= PRESENCE BIT 


C = COPY BIT 


I = INDEX BIT 


S 


= SEGMENTED 
BIT 


1 


= PRESENT IN 
MAIN MEMORY 


1 = A COPY 


1 = INDEXED 


1 


= STRING 

SEGMENTED 





= NOT PRESENT IN 
MAIN MEMORY 


= ORIGINAL 







= NOT 

SEGMENTED 


R 


= READ ONLY BIT 


SIZE = k => 8-BIT BYTE 






1 


= READ ONLY 


SIZE = 3 => 6-BIT CHARACTER 









= READ/WRITE 


SIZE = 2 =) 4-BIT DIGIT 







G-5 



(scan in) 



APPENDIX D 
SCAN FUNCTION CODE WORDS 









;.; : ! : ! : ! 


°19 




15 



11 




°7 




3 




% 




18 




14 




10 


1 

6 


2 






49 




17 



13 



9 


1 

, 5 


1 






48 



16 



12 




°B 




4 




% 



Function Code Read Time of Day Clock (OOll) 







— 




35 


31 


27 


23 


19 


15 


11 


7 


3 



50 


34 


30 


26 


22 


18 


14 


10 


6 


2 




49 


33 


?9 


TIME 6f DAY 
| 25, 21i 17 13 


9 


5 


1 




48 


32 


28 


24 


20| 16 


12 


8 


4 






Time of Day (Binary) Word Returned 













1 
19 



15 



11 


:■&%: 
•:•:••:•:= 


1 
7 




Z. 
3 






50 




18 



14 


N. 
1C 



6 


Z. 
2 






49 




17 



13 


N. 
9 


1 
5 


Z. 

1 






48 



16 



12 






8 




Z 
4 




1 





Function Code Read General Control Adapter (OlOl) 



Z = 0001, GCA A is to respond 

Z = 0010, GCA B is to respond 

Z = 0100, GCA C 

Z = 1000, GCA D 



N = 00 , Read GCA Input Register 

N = 01 , Read GCA Interrupt Mask 
Register 

N = 10 , Read GCA Interrupt Register 

N = 10 , Read GCA Output Register 



D-l 



APPENDIX D (cont) 

SCAN FUNCTION CODE WORDS 



(SCAN IN) (cont) 







47 


43 


39 


35 


31 


27 


23 


19 


15 


11 


7 


3 


50 


46 


42 


38 


34 


30 


26 


22 


18 


14 


10 


6 


2 


49 


45 


41 


37 


33 


29 


25 


21 


17 


INDEX 
13 


9 


5 


1 


48 


44 


40 


36 


32 


28 


24 


20 


16 


12 


8 


4 






a. G.C.A. Register Word Returned 



b. G.C.A. Register Word Sent To Multiplexor 












19 



15 




11 






7 





3 

Z 
2 






50 

°49 
°48 




18 



14 




10 


1 
6 




°17 


°13 


°9 


°5 


Z 
1 





16 



12 






8 




Z 

4 




1 




Fu 



notion Code Read Result Descriptor (OOIO) 



D-2 



(SCAN IN) (cont) 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



50 ; 



49. 



48 



47 



46 



45 



44 



43 



39 



35 



42 38 34 30 



31 



IMEMORY ADDRESS 
41 37 33 29 



40 



36 



32 



28 



C.C 
271 



C.C. 
26t 



C.C 
2% 



U.N. 
24 



U.N. 
23 



IU.N. 
22 



U.N, 
21 



U.N. 
20 



U.N 
19 



U.N 
18 



U.N, 
17 



16 



15 



11 



14 10 



ERROR FIELD 
13 9 5 1 



12 



Result Descriptor Word Returned 

Bit = Exception 

Bit 1 = Software Attention 

Bit 2 = Busy 

Bit 3 = Not Ready 

Bit h — Descriptor Error 

Bit 5 = Memory Address Error 

Bit 6 = Memory Parity Error 

Bit 16 = Memory Protection Error 

Bits 15:9 are Unit Error Field (see MPX section) 











! 

i 19 



15 



11 




1 
7 






3 




°50 


!°18 



14 


°,£ 


W&i 


°6 


z 2 




°49 


!°.7 



13 




' 9 


°5 


Z 
1 





48 


: 
i 16 



12 



8 


:■!;:;:•:; 



4 




1 




Function Code Read Interrupt Mask (lOlOO) 



D-3 



(SCAN IN) (cont) 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



'50 



49 



48; 



TO' 

9 5 



Interrupt Mask Word Returned. 



Bit 9 = Multiplexor I/O Finish 

Bit 1 = Data Comm. Processor 1 

Bit 2 = Data Comm. Processor 2 

Bit 3 = Data Comm. Processor 3 

Bit h — Data Comm. Processor h 

Bit = Status Change 












. 19 



15 



11 




1 

7 





3 





50 




1? 



14 




10 




6 


Z. 

2 





49 


: 
17 




13 





9 



5 


Z. 

1 




°48 



16 



12 




8 






4 




1 




Function Code Read Interrupt Register (0100) 













7 


3 



50 


6 


? 



49 




INT. 
9 


REG 

5 


STER 

1 



48 


8 


4 






Interrupt Register Word Returned 



D-4 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



(SCAN IN) (cont) 



Bit 9 = Multiplexor i/O Finish 

Bit 1 = Data Comm. Processor 1 

Bit 2 = Data Comm. Processor 2 

Bit 3 = Data Comm. Processor 3 

Bit k - Data Comm. Processor k 

Bit = Status Change Interrupt 



50 



49 



48 



19 



18 



17 



14 



15 



14 



13 



11 



11 



10 



! 1 



L. 



Function Code Read Interrupt Literal (llll) 




Interrupt Literal Word Returned 



Bits 1:2 



01 = Multiplexor A 
10 = Multiplexor B 



Bits l:h = 


= 0001 


= 


D.C.P. 


1 




0010 


= 


D.C.P. 


2 




0011 


= 


D.C.P. 


3 




0100 


= 


D.C.P. 


h 




1001 


= 


i/O Finished 




1111 


— 


Status 


Change 



D-5 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



(SCAN IN) (cont) 



50 



49 



48 



: 



19 



17 



16 



15 



14 



13 



12 



:■ N. 



11 



N. 



N. 



\ 6. 



i 



M. 



M 
M 
Z 
Z 

N 



Function Code Interrogate Peripheral Status (OOOl) 

= All Multiplexors to respond 

1 = Multiplexor designated by Z to respond 
01 = Designates Multiplexor A 

10 = Designates Multiplexor B 

=) 7 Status Vector Number (in Binary) 













31 


27 


23 


19 


15 


11 


7 


3 






50 




30 


26 


< 
22' 


5TATU 
18 


S BIT 
14 


S 

10 


6 


? 



49 






29 


25 


21 


17 


13 


9 


5 


1 




48 




llll 


32 


28 


24 


20 


16 


12 


8 


4 




X. 





Unit Status Word Returned 



X = O = Status word not present 
X = 1 = Status word present 



D-6 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



(SCAN IN) (cont) 












19 




15 


— — 
11 




1 

7 





3 


WW& 



50 



18 


UNIT 
14, 10 


1 
6 


Z. 
2 



49 



17 


NUMBER 
13 9 




5 


Z. 

1 



48 






16 


12 






8 






4 




M. 




Function Code Interrogate Peripheral Type (OHO) 










50 





49 





48 





T.C. 
* 5 



T.C 



T.C. 
3 



T.C, 



T.C, 



T.C, 



Unit Type Word Returned 



T.C. = 00 = No Unit 

01 = Disk File 

02 = Display 

Ok = Paper Tape Reader 

05 = Paper Tape Punch 

06 = Line Printer, Buffered, BCL drum 

07 = Line Printer, Unbuffered, BCL drum 

08 = Card Reader 
OA = Card Punch 

OB = Magnetic Tape (7 track) 

OC = Magnetic Tape (9 track NRZ ) 

OD = Magnetic Tape (9 track P.E.) 

ID = Magnetic Tape (7 track) 

IE = Magnetic Tape (9 track NRZ ) 

IF = Magnetic Tape (9 track P.E.) 



Exchange 



Serial or Cluster 



D-7 



(SCAN IN) (cont) 

T.C. (cont) = 26 
27 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



Line Printer, Buffered, EBCDIC drum 
Line Printer, Unbuffered, EBCDIC drum 



M 



49 



48 












19 




15 


11 





7 







3 





50 




18 


UNIT 
14| 10 



6 


Z. 


2 



49 




17 


NUMBER 

1 T o 



5 


Z. 

1 



48 










16 


12 


\=% 




8 





4 




M. ■ 




Function Code Interrogate Input/Output Path (OOOO) 



19 



17 



16 



15 



11 



UNIT 
14, 10 



NUMBER 
13 9 



12 



Input/Output Path Word Returned 



A = = No Path Available 

A = 1 = Path is Available 

Z = 01 = Path via Multiplexor A 

Z = 10 = Path via Multiplexor B 

Z = 11 = Path via Either Multiplexor 



M 



Z. 



z. 



D-J 



APPENDIX D (cont ) 
SCAN FUNCTION CODE WORDS 



(SCAN out) 












19 



15 



11 





7 


XyX'XvXy. 


3 


; 



50 



18 



14 



10 


1 
6 


2 



49 



17 



13 



9 


1 

5 


1 



48 



16 



12 





8 




4 









Function Code Set Time of Day Clock (OOll) 











35 


31 


27 


23 


19 


15 


11 


7 


3 



50 


34 


30 


26 


22 


18 


14 


10 


6 


2 



49 


33 


29 


25 


TIME OF DAY 
21 17 13 


9 


5 


1 



48 


32 


28 


24 


20 


16 


12 


8 


4 






Time of Day Word (Binary) To Multiplexor 





:•:•:!:■:•:• 






1 










1 




Z. 


li|!jj|ji 










19 


15 


11 






7 




3 















N. 







Z. 


50 








18 


14 




10 




6 




2 





49 



17 



13 


ill 


N. 
9 


1 
5 


Z. 

1 




















Z. 




l 


48 


•llll^iiii 






16 


12 


£11111 


8 


'*ViYfi'I''*'"'''*'' 


4 


::i:ii:': : : : 






Function Code Set General Control Adapter (OlOl) 



D-9 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



(SCAN OUT) (cont) 



z 


= 


OOOl 


z 


= 


0010 


z 


= 


0100 


z 


= 


1000 


N 


= 


00 


N 


"= 


01 


N 


= 


10 



GCA A is to Respond 

GCA B is to Respond 

GCA C 

GCA D 

Set GCA Output Register 

Set GCA Interrupt Mask Register 

Set GCA Interrupt Register 





W$\ 







19 



15 



11 


iliii! 


1 
7 





3 


(HI! 



50 



18 



14 



10 



6 


Z. 
2 



49 



17 



13 



9 



5 


Z. 

1 



48 



16 



12 





8 





4 




1 





Function Code Set Interrupt Mask (OlOO) 



50 



49 



48 



MASK 



Interrupt Mask Word Sent To Multiplexor 

Bit 9 = Multiplexor 

Bit 1 = Data Comm. Processor 1 

Bit 2 = Data Comm. Processor 2 

Bit 3 = Data Comm. Processor 3 

Bit h = Data Comm. Processor 4 

Bit = Status Change Interrupt 



D-10 



APPENDIX D (cont) 
SCAN FUNCTION CODE WORDS 



(SCAN OUT) (cont) 



























•v.v. 


VyV. 





•>/>>>>:■>>:•: 










19 


W$M 


15 


11 






7 






3 


: : : : x : : : : : : : :> : ; : : 















Z. 


50 








18 




14 


10 






6 






2 


MM 

















Z. 


49 








17 


W$/M 


13 


9 






5 






1 


■XvX-XvX-! 





























1 


48 


wtm 




16 


12 






8 






4 


ijjj-jjijijli: 






Function Code Initiate I/O (OOOO) 











39 


35 


31 


27 


23 






19 


15 


11 


7 


3 







BUFFEF 








AREA 




50 








38 


34. 30 


26 


22 






18 


14. 10, 6 


2 







i 
LENGT 


H 






1 ■ 
BASE ADDRESS 




49 








37 


33 29 


25 


21 






17 


13 9 5 


1 

























48 


ijii-iiiijijij 






36 


32 


28 


24 


20 






16 


12 


8 


4 






Area Descriptor Word Sent To Multiplexor 



D-ll 



APPENDIX E 
DATA REPRESENTATION 



CODES. 







BCL 


BCL 


EBCDIC 


HEXADECIMAL 




GRAPHIC 


EXTERNAL 


INTERNAL 


INTERNAL 


GRAPHIC 




Blank 


01 0000 


11 0000 


0100 0000 


40 




• 


11 1011 


01 1010 


0100 1011 


kB 




[ 


11 1100 


01 1011 


0100 1010 


kA 




( 


11 1101 


01 1101 


0100 1101 


4d 




< 


11 1110 


01 1110 


0100 1100 


kc 




*- 


11 1111 


01 1111 


0100 1111 


kF 




& 


11 0000 


01 1100 


0101 0000 


50 




$ 


10 1010 


10 1010 


0101 1011 


5B 




•X- 


10 1100 


10 1011 


0101 1100 


5C 




) 


10 1101 


10 1101 


0101 1101 


5D 




f 


10 1110 


10 1110 


0101 1110 


5E 




< 


10 1111 


10 1111 


0101 1111 


5F 




- 


10 0000 


10 1100 


0110 0000 


60 




/ 


01 0001 


11 0001 


0110 0001 


61 




? 


01 1011 


11 1010 


0110 1011 


6b 




* 


01 1100 


11 1011 


0110 1100 


6C 




= 


01 1110 


11 1101 


0111 1110 


7E 




] 


01 1110 


11 1110 


0101 1010 


5A 




it 


01 1111 


11 1111 


0111 1111 


7F 




# 


00 1011 


00 1010 


0111 1011 


7B 




@ 


00 1100 


00 1011 


0111 1100 


7C 




: 


00 1101 


00 1101 


0111 1010 


7A 




> 


00 1110 


00 1110 


0110 1110 


6E 




> 


00 1111 


00 1111 


0111 1101 


7D 



E-l 



APPENDIX E (cont) 
DATA REPRESENTATION 





BCL 


BCL 


EBCDIC 


HEXADECIMAL 


GRAPHIC 


EXTERNAL 


INTERNAL 


INTERNAL 


GRAPHIC 


+ 


11 1010 


01 0000 


1100 0000 


CO 


A 


11 0001 


01 0001 


1100 0001 


CI 


B 


11 0010 


01 0010 


1100 0010 


C2 


C 


11 0011 


01 0011 


1100 0011 


C3 


D 


11 0100 


01 0100 


1100 0100 


Ck 


E 


11 0101 


01 0101 


1100 0101 


C5 


P 


11 0110 


01 0110 


1100 0110 


c6 


G 


11 0111 


01 0111 


1100 0111 


C7 


H 


11 1000 


01 1000 


1100 1000 


C8 


I 


11 1001 


01 1001 


1100 1001 


09 


x (Mult.) 


10 1010 


10 0000 


1101 0000 


DO 


J 


10 0001 


10 0001 


1101 0001 


Dl 


K 


10 0010 


10 0010 


1101 0010 


D2 


L 


10 0011 


10 0011 


1101 0011 


D3 


M 


10 0100 


10 0100 


1101 0100 


D4 


N 


10 0101 


10 0101 


1101 0101 


D5 





10 0110 


10 0110 


1101 0110 


D6 


P 


10 0111 


10 0111 


1101 0111 


D7 


Q 


10 1000 


10 1000 


1101 1000 


D8 


R 


10 1001 


10 1001 


1101 1001 


D9 


* 


01 1010 


11 1100 


0110 1101 


6D 


S 


01 0010 


11 0010 


1110 0010 


E2 


T 


01 0011 


11 0011 


1110 0011 


E3 


U 


01 0100 


11 0100 


1110 0100 


E4 


V 


01 0101 


11 0101 


1110 0101 


E5 


¥ 


01 0110 


11 0110 


1110 0110 


E6 


X 


01 0111 


11 0111 


1110 0111 


E7 


Y 


01 1000 


11 1000 


1110 1000 


E8 


Z 


01 1001 


11 1001 


1110 1001 


E9 



E-2 



APPENDIX E (cont) 
DATA REPRESENTATION 





BCL 


■■■■ BCL 


EBCDIC 


HEXADECIMAL 




GRAPHIC 


EXTERNAL 


INTERNAL 


INTERNAL 


GRAPHIC 







00 1010 


00 0000 


1111 0000 


FO 




1 


00 0001 


00 0001 


1111 0001 


Fl 




2 


00 0010 


00 0010 


1111 0010 


F2 




3 


00 0011 


00 0011 


1111 0011 


F3 




4 


00 0100 


00 0100 


1111 0100 


Fk 




5 


00 0101 


00 0101 


1111 0101 


F5 




6 


00 0110 


00 0110 


1111 0110 


F6 




7 


00 0111 


00 0111 


1111 0111 


F7 




8 


00 1000 


00 1000 


1111 1000 


F8 




9 


00 1001 


00 1001 


1111 1001 


F9 




? 


00 0000 


00 1100 


0110 1111 


ALL OTHER 
CODES (see 
notes ) 








NOTES 









a. EBCDIC 0100 1110 also translates to BCL 11 1010. 

b. EBCDIC 1111 is translated to BCL 00 0000 with an 
additional flag bit on the most significant bit 
line (8th bit). This function is used by the un- 
buffered printer to stop scanning. 

c- EBCDIC 1110 0000 is translated to BCL 00 0000 

with an additional flag bit on the next to most 
significant bit line (7th bit). As the print 
drums have 64 graphics and space this signal can 
be used to print the 64th graphic. The 64th 
graphic is a "CR" for BCL drums and a 'V" for 
EBCDIC drums. 



E-3 



APPENDIX E (cont) 
DATA REPRESENTATION 

d. The remaining I89 EBCDIC codes are translated 
to BCL 00 0000 (? code). 

e. The EBCDIC graphics and BCL graphics are the 
same except as follows: 

BCL EBCDIC 

1 / > f (single quote) 

2) x (multiply) J 

3) < (not) 

— [ 
^) r _ (underscore) 

5) - T 



E-4 



APPENDIX F 
B 6500 EBCDIC/HEX CARD CODE 





£ 


H 
00 


H 


CM 


CTN 


-3- 


in 


vo 


J>- 


00 


ON 


CM 
00 


cn 
00 


00 


in 
00 


vo 

00 


00 


!Zi 




X! 

ft 
K 


O 


H 


C\i 


en 


^t 


in 


vo 


{> 


00 


ON 


< 


PQ 





P 


ft 


ft 


X 
ft 




ft 


O 
\ 

1 c 

+ 


H 


CM 


en 


•3- 


in 


VO 


J> 


00 


0\ 














ft 


ON O 1 


+ 





ft 




W 


H 


P 


> 


Is 


X 


!* 


N 














ft 


On O 1 


1 


P 


>"0 


W 


J 


S 


£ 


^SL 


ft 


C^ 


ft 














P 


On 1 


+ 


+ 




PQ 


<J 


P 





P 


ft 


ft 


cij 


in 


H 














O 


On O 


+ 


+ 1 


O 


































P 


O 1 


+ 


1 


<! 


2 


CO 


■p 


P 


i> 


£ 


M 


>-> 


N 














<! 


O I 


+ I 


o\ 




'"-J 


# 


H 


a 


s 





ft 


U 1 


in 














On 


I + 


+ 


O 


00 




OJ 


P 


O 


■d 


CD 


«H 


£iD 


£ 


•H 














00 


O 


+ 


+ 1 


O 0\ 


j> 




















• 


•• 


=*: 


® 


- 


II 


E 


j> 




1 o\ 


vo 


1 


^1 
















Al 


- 


^ 




A 


0- 


vo 


O 


+ 1 


C\ 


in 
















"^ 


— 


=©3= 


* 


— 


.„ 


r~ 


m 


1 


+ 


O 0\ 


Jt 


fin 
















1 


VI 


^ 


O 


V 


^ 


+ 




j- 


+ 


ON 


en 




cn 










ft 
O 
ft 










-3- 
O 
P 


1 




p 
p 

cn 


cn 


On 


o\ 


cm 












ft 

ft 


ft 
ft 


O 
cn 

ft 












C3 5 

ft 


ft 



ft 
P 


CM 


ON O 


1 ON 


H 


ft 

p 


H 
O 
P 


CM 
O 

P 


cn 

P 













n 






cn 

ft 


cn 

Ci5 


cn 

ft 


cn 

P 


H 


ON 1 


+ 


0\ 


O 





K 
O 

U1 


cn 


XI 








ft 
P 










ft 
ft 


ft 
O 




cn 


H 

cn 





ON 


+ 


N O 


E ft 


X! 
ft 


H 


CM 


en 


-3- 


m 


VO 


J> 


00 


On 


<d 


ft 


O 


P 


ft 


ft 


X 
ft 


N £ ft 


& 


H 
CO 


H 


CM 


en 


•a- 


m 


vo 


*>■ 


00 


H 
00 


CM 

00 


cn 
00 


■3" 

00 


m 
00 


vo 
00 


00 


£ 



F-l 



APPENDIX F (cont) 
B 6500 EBCDIC/HEX CARD CODE 

Use of the B 65OO EBCDIC/HEX Card Code Chart. 

a. Locate the desired EBCDIC graphic code within the table. 

b. The two-part Hexadecimal Code is read as follows: 

1) The first part is found in the vertical column 
above or below the desired EBCDIC code. 

2) The second part is found in the horizontal row 
either to the right or left of the desired EBCDIC 
code . 

a ) Examples : 

SYN = 32 
F = C6 

c. The two-part Card Code is found in the same manner as HEX 

(b) except the zone and numeric bits are read from the 
very outer portion of the table. 

1 ) Examples : 

SYN =92 
P = + 6 

2) The card code exceptions to the above procedure 
are enclosed in heavy lines on the chart and are 
defined below: 

a) 00 = + 0981 (NUL) 

b) 10 = + -981 (DLE) 

c) 20 = - 0981 

d) 30 = + -0981 

e) 40 = BLANK 

f) 50 = + (&) 

g) 60 = - (-) 



F-2 



APPENDIX F (cont) 
B 6500 EBCDIC/HEX CARD CODE 



h 


) 70 = 


+ - 









i y 


) CO = 


+ 




({) 


(i) 


j] 


) DO = 


- 




(}) 


(z) 


k] 


) EO = 





82 


(\) 




I] 


) FO = 







(0) 




m j 


61 = 





1 


(/) 




n] 


El = 


-09 


1 






] 


6A = 


+ - 




(!) 





F-3 



APPENDIX G 
HEXADECIMAL- DECIMAL CONVERSION TABLE 



The table in this appendix provides for direct conversion of 
decimal and hexadecimal numbers in the ranges: 



Hexadecimal 



000 to FFF 



Decimal 
to 4095 



For numbers outside the range of the table, add the following 
values to the table figures : 



Hexadecimal 

1000 
2000 
3000 
4000 

5000 

6000 

7000 

8000 
9000 
A000 
B000 
C000 
D000 
E000 
F000 



Decimal 

4096 

8192 
12288 
16384 
20484 
24576 
28672 
32768 
36864 
40960 
45056 
49152 
53248 
57344 

61440 



G-1 



in h s n 
u. «-• po & so 



O CV ro un 

cm (\i cm cm 



vi r-. ro o 

K OO O « 

N N n »o 



in — r 
ro m 
ro ro 



sO |s- O vi 



<* o %o cm 

Ul «-t ro <» so 



r- o «-i cm 



in r- o>> 



<3 tv oo ^» 
o cvi ro m 

CM CM CM CM 



o no cm oc 

r- OC O *-« 

cm cm ro po 



o vi ro 



sc r- o — 



ro o* tfi <h 
q vi cm «r so 



in n. co o cm ro m 
«-««-<«-• cm cm cm cm 



o m «-» n. 

so oo o — < 

CM CM ro PO 



ro O U"i — ' 

m ij « o 
PO ro ro fO 



ro o> m 



O vl CM 



v« N- 
so N- 



cm oo «r o 

o «-» cm <ar o 



sO CM 00 



O O CM 



O sO CM 00 

«* in »»- to 



CM ro in 



vl v> vt CM CM CM CM 



CM cm ro ro 



ro qr so ao 
ro oo rO' ro 



O vi CM 



O sO CM CO 
so r- O 



o> 


in 


<-i 


p~ 


ro 


O 


in 


V* 


ro 


in 


rw 


00 


O 


VI 


ro 


in 


«-* 


•-< 


«-t 


vl 


CM 


CM 


CM 


CM 



SO 00 O vl 

CM CM CM ro 



•-• N- ro CT» 
ro •=» «o r~ 
ro ro ro ro 



O so CM 00 

«i «* cm <r m 



oo <r o so cm oo «»■ 

romr-.ec* O v i ro 

vi vi rt v) CM CM CM 



« W B 9 

>c cc o --. 

CM CM CM ro 



0> «-i CM 



ro ro ro ro 



o» in «-• r- 

0K N 4 IT 



ro o in — « 
r- oc O CM 



f>- ro o in 
ro in so oo 



o rt m 



— » CM CM CM CM 



K. ro 



CM CM CM 



o» in «■« r- 



ro ro ro ro 



ro o in «-' 



r- ro o in 
in r- to o 



CO <» O so 

cc cv «r m 



CM CO <» O 

r~ 00 O CM 



O so CM 00 

o «-« ro <r 

— • «-« «-t CM CM CM CM 



CM CM CM PO 



ro ro ro 



K. ro o> in 

r-. CV ro in 



IP v* r«. ro 
ro m «o ao 



c/> m «h 
O — i ro 
vi CM CM 



«-t r- ro 



CM CM CM ro 



ro ro ro ro 



1/1 K O) 



O W CD> » 
so CM ro in 



4 9 <0 OH 

ro m <o oo 



co -=r o so 



O K o «-i 
CM CM CM ro 



« ftl 0D 



ro ro ro 



sf) CM CO 



«■ «D so CW 



in «-< r-. ro 
in cv ro in 



O in «-• r- 
«o oo o *-< 



ro o m vt 
ro <» so oo 



p-room •-« k. o o 
o •-• cm <»■ sO K. O O 

r" N N N CMCMCMCO 



CM «T in N- 
ro ro ro ro 



oo o CM ro 



ro o- 
m so 



in «-» 
oo o 



*r o so cm 
<r cm ro ip 



cm oo 4- o 
po ^- so oo 



0» n CM 



CM CM CM 



sO r- 
CV CM 



NO CM CO 



* O sO CM 

cm <*- in r-. 

ro ro ro ro 



in %o oc 



ro c- iT. — 
ro «-< ro m 



ro os in 

so o M 



vi rw po o> in «-i r>- PO 

PO«\Or~ O vt CM «» 

■H vi vi vi vi CM CV CM 



CM CM CM fO 



ro o 
CM PO 

ro ro 



ro o« in 



vi r- PO o 

in \o oo o> 



cm s <r o 

CM vi ro in 



SO CM 
sO 00 



O vO Cvi CC 



O — « CM 



CM CV CM 



in r- 

CM CM 



CM CO 

CM ro 
ro ro 



CM CO 



in vo oo 



sO CO O vi 



o in « 
cm «■ so 



ro cjv in ih 

o o cv <* 



vi vi vi vt CM CV 



in v» p^ po o 



CV CV CM P0 



in vi p-. 

00 O vi 



0> Ifl <h K 

<r so oo o 



o 

X 

Q 



O sO CM OO 

O w ro 9 



so OC O vi 



CM s» sO 



CM CM CM 



O so CM 00 



cm cm cm ro 



o o o o 

O v* CM PO 

o o o o 



O vi CM ro 



» HI « 



G-2 



r>~ oo ck m 

cm <t in r~ 
m in m m 



«-• K. m o* 

O O CM OO 

in o « « 



in »-• k. 
m k~ <o 
nD no no 



ck m —« n- 
*-> ci jr\ \o 

s. r»- r»^ N- 



oo o> m «-« 
co ck «-i on 
n- r«^ oo oo 



r~ f> o in 

* « N » 
00 00 0O 00 



«-• cvi «r 
o o o 



m «-< v- m 

N- O O CM 

» ck o o 



no cm oo «*■ 

cm «■ m r~ 
in m in tr> 



O NO CM 00 
O O CM ro 

in <o « « 



<r o no cm 

in r- oo o 
no no no K. 



co <r o no 

»-> oo in \o 

K- r^ N- r~ 



w oc <r o 

oo o «-H CO 

K K «C CD 



<o cm oc «r 
*r <© r- o 

00 00 00 CD 



O O CM 
»-> CM «f 

» o> a 



«• O nD CM 

^ ck o cm 

CK O O O 



m «-• s- m 

ft; « in s 
in in m m 



o m «-h n- 

co o CM ro 
in <o -o o 



♦*i ck in *-• 
in no co o 
no no no t^ 



K. en o\ m 



*■« r— m o 

CO O *H CM 

K. Kw CO OC 



in •-« K- oo 
** no r~- o 

00 00 00 CO 



o» o o> 



on ck in »-< 

t>- 00 O CM 

ck ck o o 



<»• O n£> CM 

N 9 in N 

in m tn in 



oo <r o « 
oo o cm on 

in no no no 



cm oo <r 
in « o 
so no no 



NO CM 00 



O NO CM 00 

00 CK «-i CM 
N- S- 0O 00 



«r o o cm 

cr no N- O" 
CO CO OO 00 



co •» o 
o cm <=r 
ck o> » 



CM 00 

r>- co 



oo ov in — « 
cm oo m r>- 

m m m m 



r>. m r> in 

oo O »"i ro 

m no no * 



>H S P«) (Ji 

in « co o 

NO NO NO NO 



in «■* r»~ oo 



o in •-! n. 

k- o »-< CM 

K N. K) K 



on ck in »-» 
<r in n- o 

oo CO CO CO 



K«- on c?v in 
o cm on m 

o » oi oi 



cm oo <r o 

cm rn m is. 
in in in in 



\o cm oo «r 

OO O «~l oo 

in o o no 



O nD CM 00 

in « c » 

nO nO NO no 



•"a- o no cm 

«-« oo *r no 

K. r- N. (w 



CO <? O nO 

N W ^ (V 
K k OD O 



CM 00 «■ O 

«r m r~ ck 

00 00 GO CO 



« (VI CO <t 

o cm m m 
ck ck ck ck 



O nO CM oo 

K. ao o i— 

o» ck o o 



«-» K>~ 00 CK 

cm »»v m vi 
m m in in 



in «-< r^ on 
co o «-> rn 
in >o no <o 



o in »-< fw 
*» no «o o> 
no no no nd 



oo o> in »-» 

»-» cm <r nd 

K~ rt. r<~ N. 



N- on o m 

t*- <7> O CM 
N- h- CO 0O 



«* n- on o» 
<s- un N- 00 
oc oo co oo 



in »< k m 
o cm oo m 
o> o> o> o> 



o m «i k. 
o oo o «-« 
inx o o o 



o «o CM 00 
cm oo m »o 
m in in m 



«• o « CM 
oc o «-« oo 
in <o no o 



oo <» o o 

«- «o CO o> 

<0 »0 "O O 



CM 00 

—i CM 



«o cm oo *r 

r~ O* O CV 

N- S 00 » 



O M3 CM OO 
<* lO N- 00 
CO CO CO CO 



«■ O «0 CM 

o cm oo m 
o"> o cr> o 



« oc o — 
CT> 0> O O 



o* in — « n- 
•-< on m >o 
in in m m 



oo o m «-» 
co o> •-* on 

in in o o 



k- oo o> in 
«• \o n. o> 

«0 «0 vO O 



»i h» on o« 
-hi cm <t in 

h- ^ h_ >^ 



m *-• k- o 
n- o o cv 

N- K C B 



o\ m «-> k. 

n m k o 

OO CO CO oo 



n o« in « 
o »< oo m 
o> o c* o> 



r«- oo o» in 
<o CO o «-i 

Oi o> O O 



oo «r o vo 

»• n in o 
in m in m 



CM qr o 
oo ok v-t <n 
in m o o 



<o cm oo <r 
«• \o k. o» 
o «o >o «o 



O « CM CO 

*- cm «r tn 

N S N N 



«r o »o «i 
f- o^ o CM 

N K W CO 



a « o « 
fn in k. oo 

00 OO CO CO 



CM OO J» o 

o T< ci m 

O O O- CK 



» cm oo *r 

vO co o> •■ h 

CK 0> CK O 



n. oo ck in 

<i m <r « 
in m m in 



i s n o> 

CO 0> —i CM 

in m xo \o 



m »-« h^ oo 
«r <o n. o> 
o >o >o o 



t> in »-• k 
o cv «r m 



oo o> in m 

N. CO O CM 

N- ^ 00 CO 



r- oo c tn 
oo m o so 
00 00 oo oo 



•-i k. m o 
o •-* oo «r 
o> O s OK 



m «-< ^ m 
so oo o* — < 
o> o o> o 



O CM OO <* 

•i on «• \o 
in in m in 



O vO CM CO 
00 O »-i CM 

in in vo >o 



«r o vo cm 



NO NO NO NO 



oo «r 
o cv 



cm co «r o 

N- CO O CM 

K K IO 09 



no cm co «r 
oo m no co 
oo co co co 



O NO CM CO 

o ^-t oo <r 

O CK CK Ch 



«■ O NO CM 
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ro ro ro ro 



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ro co ro co 



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ro ro ro ro 



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ro ro ro ro 



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ro ro ro ro 



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ro ro ro ro 



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r>- » «-!> 

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ro ro ro ro 



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w-t cv «r >o 

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ro ro ro ro 



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nO no no r«. 
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cv ro in no 



ro ro ro ro 



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ro ro ro ro 



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nO no no r- 
ro ro ro ro 



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ro ro ro ro 



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oo oo oo oo 
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NO 


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ro ro ro ro 



(NO 0> in NT-t 

N-» CV «*• NO 

r- r- r- r~ 

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r~ o> n-4 CV 
r- f- CO CO 
ro ro ro ro 



00 «r O no 

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N- N- CO 00 

ro ro ro ro 



ro ro ro ro 



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r» N. 0O CO 

ro CO CO CO 



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«r no n. o> 

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0> On 
ro ro 



r- ro o- 



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ro m 



room-TH pN-rooin ^-trv-rooN 



oo oo oo oo 
ro ro ro ro 



cr in k- on 

00 OO 00 00 

ro ro ro ro 



N»-t r». ro o 

« in in. to 

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ro ro ro ro 



O no CV CO 



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© CM ro in 
On O On O 
ro ro ro ro 



N. CO © «-• 



NO CM CO 



cv ro m *- co o »-• 



On 


O 


O 


On 


ro 


ro 


ro 


ro 


in 


** 


r~ 


ro 


o 


CV 


ro 


in 


o 


On 


On 


0> 


ro 


ro 


ro 


ro 


«• 


O 


nO 


CV 


o 


CV 


ro 


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ON 


ON 





ro 


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© «-< 
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G-9 



INDEX 



Absolute Address Conversion, 3-20 

Adapter Cluster, 11-3 

Add, 7-2 

Adder High Speed, 5-6 

Address Adder, 5-40 

Address Environment , 3-21 

Address Word , 10-3 

ADJ (Op) Switch, 4-18 

Alarm Interrupts , 5-21 

Alpha Card Read, 5-35 

Area Descriptor, 8-16 , 10-3 

A Register, 4-1 

Arithmetic Control, 4-5 

Arithmetic Operators , 7-1 

Auxilliary Cabinet , 1-6 

Base and Limit of Stack, 3-2 

Base of Addressing-Level Segment , 
3-20 

Binary Card Read, 5-35 

Bit Operators , 7-19 

Bit Reset , 7-19 

Bit Reset Dynamic , 7-20 

Bit Set, 7-19 

Bit Set Dynamic , 7-19 

Bit Sign Change , 7-20 

Bottom of Stack, 5-13 

Branch False, 7-10 

Branch False Dynamic , 7-11 

Branch Operators , 7-10 

Branch True, 7-10 

Branch True Dynamic , 7-11 

Branch Unconditional, 7-10 

Branch Unconditional Dynamic , 7-li 

B Register, 4-1 



Card Load Operation, 4-33 

Card Punch, 10-10 

Card Reader, 10-7 

Channel Assignment Control , 
5-31 

Character Codes , Internal , 2-1 

Character Translator, 5-31 

Character Type Data, 2-8 

Clear and Halt Load, 4-12 

Clock Controls , 4-15 

Clocks , 1-9 

Coded to Decimal Conversion, 
2-4 

Command Data Register, 5-29 

Compare Characters Equal De- 
structive, 7-28 

Compare Characters Equal Up- 
date, 7-28 

Compare Characters Greater " 
Destructive, 7-27 

Compare Characters Greater or 
Equal Destructive, 7-28 

Compare Characters Greater or 
Equal Update, 7-28 

Compare Characters Greater 
Update, 7-27 

Compare Characters Less De- 
structive, 7-28 

Compare Characters Less or 
Equal Destructive, 7-28 

Compare Characters Less or 
Equal Update, 7-28 

Compare Characters Less Update t 
7-28 

Compare Characters Not Equal 
Destructive, 7-29 

Compare Characters Not Equal 
Update, 7-29 

Conditional Halt , 7-12 

Conditional Halt Switch, 4-17 



one 



INDEX (cont) 



Console , 10-5 

Controller, Interrupt, 4-8 

Memory, 4-9 > 5-36 

MPX, 5-36 

Program , 4-10 

Stack, 4-9 

String- Operator, 5-25 

Transfer, 4-11 



Controller 
Controller 
Controller 
Controller 
Controller 



Controller 

Control Panels , 4-1 

Control State, 1-12 

Control State/Normal State, 5-27 

Copy Bit , 3-5 

Count Binary Ones , 8-23 

C Register, 4-2 

Data Addressing, 3-3 

Data Communications Adapters, 1-22 

Data Communication Interface, 5-33 

Data Communications Interrupt , 5-20 

Data Communications Processor, 
1-21, 11-1 

Data Communications System, 11-1 

Data-Dependent Presence Bit , 5-l4 

Data Descriptor, 3-3 

Data Representation, 2-1 

Data Switching Channels , 1-18 

Data Types and Physical Layout , 

2-8 

Decimal to Coded Number Conversion, 
2-4 

Decimal to Hexadecimal Table Con- 
version, 2-5 

Delete Top of Stack, 7~l4 

Description of Units, 1-1 

Descriptor Formats , 10-2 



Detect Mode (MDP) , 5-34 

Diagnose Mode (MDP) , 5-34 

Disable External Interrupts, 
8-2 

Disk File Subsystems, 10-20 

Disk Load Operation, 4-34 

Display Mode (MDP ) , 5-34 

Display Select Switches , 4-l4 

Divide, 7-4 

Divide by Zero Interrupt, 5-H 

Duplicate Top of Stack, 7-l4 

Dynamic Branch False , 7-H 

Dynamic Branch True, 7-H 

Dynamic Branch Unconditional, 
7-11 

EBCDIC Card Read, 5-36 

Edit Mode Operation, 9-1 

Edit Mode Operators , 9-1 

Enable External Interrupts, 8-2 

End Edit , 9-6 

End Float , 9-4 

Enter Operator, 7-36 

Equal, 7-9 

Evaluate, 7-36 

Exchange, 7-13 

Execute Single Micro Destruc- 
tive, 7-30 

Execute Single Micro Single 
Pointer Update, 7-30 

Execute Single Micro Update, 7-30 

Executing I/O Descriptors, 4-29 

Exit Operator, 7-36 

Exponent Overflow and Underflow 
Interrupt, 5-H 



two 



INDEX (cont) 



External MPX Interrupt , 5-21 
EXT-I Switch, 4-17 

Family A , 4-5 

Family B, 4-6 

Family C , 4-6 

Family D , 4-6 

Family E , 4-7 

Features, Processor, 1-13 

FF Reset Switch, 4-l6 

Field Insert, 7-22 

Field Insert Dynamic , 7-22 

Field Isolate, 7-21 

Field Isolate Dynamic , 7-21 

Field Transfer, 7-20 

Field Transfer Dynamic , 7-21 

General Control Adapter Interrupt , 
5-21 

Greater Than, 7-9 

Greater Than or Equal, 7-9 

Halt Load and Load Select Switches , 
4-16 

Halt Switch, 4-32 

Hexadecimal Notation, 2-2 

Hexadecimal to Decimal Table Con- 
version, 2-5 

Idle Until Interrupt, 8-2 

Index, 7-15 

Index and Load Name, 7-l6 

Index and Load Operators , 7-15 

Index and Load Value, 7-l6 

Index Bit , 3-4 

Index, Invalid, 3-4 



Index, Valid, 3-k 

Indicators BO, Bl , B2 , 4-15 

Indirect Reference Word, 6-l4 

Information flow (Card Reader 
to Memory) , 5-35 

Initiate i/O , 8-15 

Input Convert Destructive, 7-31 

Input Convert Operators , 7-31 

Input Convert Update, 7-32 

Input/Output Multiplexor, 1-17 > 

5-29 

Insert Conditional, 9-5 

Insert Display Sign, 9-5 

Insert Mark Stack Operator, 
7-40 

Insert Overpunch, 9-5 

Insert Unconditional, 9-4 

Integer Divide, 7-4 

Integerized Rounded D.P. , 8-19 

Integerize Rounded, 7-6 

Integerize Truncated, 7-5 

Integer Overflow Interrupt , 
5-13 

Integrated Chip Memory, 5-40 

INT-I Switch, 4-17 

Internal Character Codes, 2-1 

Internal Data Transfer Section, 

5-3 

Interrogate i/O Path, 8-12 

Interrogate Peripheral Status , 
8-9 

Interrogate Peripheral Unit 
Type, 8-10 

Interrupt Controller, 4-8, 5-8 

Interrupt Handling, 1-14, 5-25 

Interrupt Network, 5-31 



three 



INDEX (cont) 



Interrupt Other Processor, 8-17 

Interrupt System, 1-13 

Interrupts, Alarm, 5-21 

Interrupts, External, 1-16 , 5-17 

Interrupts, Operator Dependent, 
1-15, 5-9 

Interrupts, Operator Independent, 
1-15 

Interval Timer Interrupt , 5-18 

Invalid Address Interrupt, 5-24 

Invalid Index Interrupt , 5-12 

Invalid Operand Interrupt , 5-11 

Invalid Operator, 7-12 

Invalid Program Word Interrupt , 
5-24 

I/O Control Word, 10-3 

I/O Descriptor, Execute Recycle, 
4-30 

I/O Descriptor, Execute Single 
Cycles, 4-29 

I/O Finished Interrupt , 5-20 

i/O Operations , Processor Initi- 
ated , 1-21 

Job-Splitting, 3-22 

Keyboard Control Keys , 4-36 

Leading One Test , 8-19 
Less Than, 7-10 
Less Than or Equal , 7-9 
Level Definition, 3-22 
Line Adapter, 11-5 
Line Printer, 10-12 
Linked List Lookup, 8-23 
Lit Call Zero , 7-l4 



Lit Call One, 7-l4 

Lit Call 8 Bits , 7-l4 

Lit Call 16 Bits, 7-l4 

Lit Call 48 Bits, 7-l4 

Literal Call Operators, 7-l4 

Load , 7-16 

Load Select Switch, 4-33 

Load Switch, 4-33 

Load Transport , 8-23 

Local/Remote Switch, 4-18 

Logical And , 7-8 

Logical Equal, 7-9 

Logical Equivalence, 7-8 

Logical Negate, 7-8 

Logical Operands , 2-12 

Logical Operators , 7-8 

Logical Or, 7-8 

Logic Card Testing, 4-32 

Loop Interrupt , 5-22 

Magnetic Tape Subsystems, 10-14 

Main Memory, 1-16 , 5-4l 

Maintenance Control General, 
4-11 

Maintenance Diagnostic Proces- 
sor, 5-34 

Make PCW , 7-15 

Mantissa Field, 2-10 

Mark Stack Control Word, 6-10 

Mark Stack Control Work Link- 
age, 3-16 

Mark Stack Operator, 7-40 

Mask and Steering, 5-5 

Mask and Steering Example, 5-6 



four 



INDEX (cont) 



Masked Search for Equal , 8-24 

Master Control Program, 1-9 

MDL Control Switches , 4-l4 

MDL Register Clear, 4-l4 

MDTR/Normal Switch, 4-15 

Memory Addressing, 5-46 

Memory and MPX Controller, 5-36 

Memory Area Allocation, 3-l4 

Memory Bus , 5-39 

Memory Cabinet Configuration, 5-43 

Memory Controller, 4-9 

Memory Cycle Times, 1-17 

Memory Exchange, 5-31 

Memory Interface, 5-43 

Memory Interlacing, 5-46 

Memory Organization, 5-4l 

Memory Parity Interrupt , 5-22 

Memory Priority, 5-43 

Memory Protect Interrupt, 5-10 

Memory Protection, 5-42 

Memory Registers, 5-46 

Memory Second Level , 1-17 

Memory Stack Controller, 5-47 

Memory Tester, 4-40 

Memory Tester Non-Test Operation, 
4-41 

Memory Tester Test Operation, 4-4l 

Memory Testing, 5-47 

Memory Words , 1-17 

Move Characters , 9-1 

Move Numeric Unconditional, 9-2 

Move TO Stack, 8-19 

Move With Float, 9-3 

Move With Insert, 9-2 



MPX Maintenance Control Panel, 
4-26 

MPX Operation, 10-1 

MPX Parity Interrupt , 5-22 

Multiple Stacks and Re-Entrant 
Code, 3-22 

Multiple Variables (Common Add- 
ress Couples), 3-20 

Multiplexor Configuration, 1-17 

Multiplexor, Input/Output , 1-17 

Multiplexor Interrupts , 5-19 

Multiplexor Register Clear, 
4-14 

Multiplexor Registers and Flip 
Flops , 4-22 

Multiply, 7-3 

Multiply (extended), 7-3 

Name Call, 6-3, 7-33 

No Operation, 7-12 

Normal/Control State Switches, 
4-18 

Normal State, 1-12 

Not Equal, 7-10 

Number Bases, 2-2 

Number Conversion, 2-4 

Occurs Index, 8-17 

Octal Notation, 2-2 

Operands , 2-9 

Operation Types , 6-2 

Operators Control Console , 4-32 

Operator Dependent Interrupt , 
5-9 

Operator Families , 5-1 

Operator Independent Interrupts , 
5-17 



five 



INDEX (cont) 

Operator Panel, 4-32 Presence Bit Interrupt, 3-24 

5-13 



Operators , 6-3 

Operators Introduction, 2-12 



Primary Mode Operators , 7-1 
Priority Handling Example, 5-19 



Options and Requirements Tor 

System, 1-5 Priority Handling with IIHF 



Order of Magnitude , 2-7 
Overflow FF , Read and Clear, 7-32 
Overwrite Destructive, 7-13 
Overwrite Non-Destructive, 7-13 

Pack Destructive, 7-30 



set, 5-20 

Procedure-Dependent Presence 
Bit , 5-14 

Processor, 1-12 

Processor Features , 1-13 

Processor Initiated I/O Opera- 
t ions , 1-21 



Pack Operators , 7-30 _ „ . , ~ , ., 

^ Processor Maintenance Controls 

Pack Update, 7-31 (Panel E), 4-16 

Panel A, 4-1 Processor Register Clear, 4-l4 

Panel B, 4-2 Processor States, 1-12 

Paper Tape, 10-24 Processor System Concept, 5-1 

Parity Switch, 4-18 Processor to Processor Inter- 
rupt , 5-18 



Peripheral Control , 1-21 

Peripheral Control Bus , 1-19 

Peripheral Control Cabinet , 1-8 

Peripheral Control Interface, 5-33 

Peripheral Controls , 1-18 

Peripheral Units , 10-5 



Program Controller, 4-10, 5-2 
Program Control Word , 6-11 
Programed Operator, 5~^5 
Program Operators , 6-1 
Program Restai.rt , 5-15 



Polish Notation, 3-5 Program Structure in Memory, 

3-14 
Polish String, 3-8 pulse Tra±n Swltch> k _ ±5 

Polish String, Rules for evalu- push Down stack R isters , ? _ l4 

atmgj 3-8 

Polish String, Rules for gener- _. , __,. ,, 
„ _ Read GCA , 8-4 

atmg, 3-7 

„ _, ., ., „ Read IC Operation, 4-19 

Power Controls , 4-12 ^ 

t> ^n. c . , , /, oo Read IC Switch, 4-18 

Power Off Switch, 4-32 

_, _ „ . , , ,, 00 Read Interrupt Literal, 8-8 

Power On Switch, 4-32 ^ 

„ _, - ^ Read Interrupt Mask, 8-6 

Power^ System, 1-6 

^ „ ,„/■-, Read Interrupt Register, 8-7 

P Register, 4-2, 6-1 

^ T-. • .<_ ^ r. Read Main Memory, 4-28 

Presence Bit , 3-4 



six 



INDEX (cont) 



Read Only Bit , 3-5 

Read Processor Identification, 
8-17 

Read Processor Register, 8-22 

Read Processor Register Switches , 
4-20 

Read Result Descriptor, 8-4 

Read SPM , 4-27 

Read Tag Field, 8-21 

Read Time of Day Clock, 8-3 

Read With Lock, 8-23 

Real Time Adapter, 1-24 

Recycle Execution i/O Descriptor, 
4-30 

Re-Entrance, 3-22 

Register, A, 4-1 

Register, B, 4-1 

Register, C, 4-2 

Register, P, 4-2 

Register, X, 4-2 

Register, Y, 4-2 

Relational Operators, 7-9 

Relative-Addressing, 3-18 

Remainder Divide, 7-5 

Reset Float , 9-4 

Result Descriptor, 10-4 

Return Control Word , 6-12 

Return Operator, 7-36 

Rotate Stack Down, 8-21 

Rotate Stack Up, 8-21 

Rules for Generating Polish 
String, 3-8 

Running Indicator, 4-33 

Scale Left , 7-17 

Scale Left Dynamic , 7-17 



Scale Operators , 7-17 

Scale Right Dynamic Final, 7-18 

Scale Right Dynamic Save, 7-18 

Scale Right Dynamic Truncate, 
7-18 

Scale Right Final, 7-18 

Scale Right Round Dynamic , 7-19 

Scale Right Rounded, 7-18 

Scale Right Truncate, 7-18 

Scan Bus , 5-29 » 5-40 

Scan Bus Control, 5-19 

Scan Operators , 8-2 

Scan Out , 8-13 

Scan While Equal, Destructive, 
8-29 

Scan While Equal, Update, 8-29 

Scan While False, Destructive, 
8-30 

Scan While False, Update, 8-30 

Scan While Greater, Destructive, 
8-28 

Scan While Greater, Update, 8-28 

Scan While Greater or Equal, 
Destructive, 8-29 

Scan While Greater or Equal, 
Update, 8-29 

Scan While Less, Destructive, 
8-29 

Scan While Less or Equal , De- 
structive, 8-29 

Scan While Less or Equal, Update, 

8-29 

Scan While Less, Update, 8-29 

Scan While Not Equal, Destructive, 
8-30 

Scan While Not Equal, Update, 
8-30 



seven 



INDEX (cont) 



Scan While True, Destructive, 
8-30 

Scan While True, Update, 8-30 

Scratch Pad Memory, 5-2-9 

SECL Switch, 4-17 

Second Level Memory, 1-17 

Segmented Array, 5-15 

Segment Descriptor, 6-9 

Set Double to two Singles , 8-1 

Set External Sign, 7-32 

Set GCA, 8-14 

Set Interval Timer, 8-2 

Set Processor Register, 8-23 

Set Tag Field , 8-20 

Set Time of Day Clock, 8-l4 

Set to Double-Precision, 7-7 

Set to Single-Precision Rounded, 

7-7 

Set to Single-Precision Truncated, 
7-6 

Set Two Singles to Double, 8-1 

Single Cycle Execution I/O Des- 
criptor, 4-29 

Single Pulse Switch, 4-15 

Skip Forward Destination Charac- 
ters , 9-4 

Skip Forward Source Characters, 
9-3 

Skip Reverse Destination Charac- 
ters, 9-4 

Skip Reverse Source Characters, 
9-4 

Stack 3-1 

Stack, Base and Limit, 3-2 

Stack, Bi-Direct ional Data Flow, 
3-2 

Stack Controller, 5-47 



Stack Deletion, 3-l6 

Stack Descriptor, 3-23 

Stack, Double-Precision Operation, 
3-2 

Stack-History and Addressing- 
Environment Lists , 3-16 

Stack History, Summary, 3-21 

Stack Operators , 7-13 

Stack Overflow Interrupt , 5-18 

Stack Registers ., 5-3 

Stack, Simple Operation, 3-9 

Stack Underflow Interrupt , 5-24 

Stack Vector Descriptor, 3-24 

Start Switch, 4-l6 

States, Processor, 1-12 

Step and Branch, 7-12 

Step Index Word, 6-l6 

Stop Switches, 4-17 

Store Destructive, 7-13 

Store Non-Destructive, 7-13 

Store Operators , 7-12 

String Descriptor, 6-7 

String Operator Controller, 5-25 

String Transfer Operators , 7-23 

Stuff Environment , 7-40 

Stuffed Indirect Reference Word, 
6-14 

Subroutine Operators , 7-32 

Subtract , 7-3 

Syllable Addressing, 6-1 

Syllable Format , 6-1 

Syllable Identification, 6-1 

System Clock, 5-33 

System Clock Control and MDL Pro- 
cessor, 5-33 



eight 



INDEX (cont) 



System Concept , 5-1 

System Description, 1-1 

System Expansion, 1-18 

System Options and Requirements , 
1-5 

System Organization, 1-9 

System Power, 1-6 

Table Enter Edit Destructive, 
7-29 

Table Enter Edit Update, 7-30 

Tag Register, 5-31 

Time of Day Register, 5-31 

Transfer Controller, 4-11 

Transfer Operators , 7-6 

Transfer Unconditional, Destruc- 
tive, 7-26 

Transfer Unconditional, Update, 
7-26 

Transfer While Equal, Destruc- 
tive, 7-25 

Transfer While Equal, Update, 
7-25 

Transfer While False Destruc- 
tive, 8-27 

Transfer While False, Update, 
8-27 

Transfer While Greater, Destruc- 
tive, 7-24 

Transfer While Greater or Equal, 
Destructive, 7-25 

Transfer While Greater or Equal, 
Update, 7-25 

Transfer While Greater Update, 
7-24 

Transfer While Less , Destruc- 
tive, 7-25 

Transfer While Less, Update, 
7-26 



Transfer While Less or Equal, Des- 
tructive, 7-25 

Transfer While Less or Equal , Up- 
date, 7-25 

Transfer While Not Equal , Destruc- 
tive, 7-26 

Transfer While Not Equal, Update, 
7-26 

Transfer While True, Destructive, 
8-26 

Transfer While True, Update, 8-27 

Transfer Words Destructive, 7-23 

Transfer Words, Overwrite Des- 
tructive, 7-23 

Transfer Words, Overwrite Update, 
7-23 

Transfer Words, Update, 7-23 

Translate, 8-27 

T Register, 6-1 

True False FF , Read, 7-32 

Type Transfer Operators , 7-6 

Unit Clear Switch, 4-18 
Universal Operators , 7-12 
Unpack Absolute Destructive, 8-25 
Unpack Absolute Update, 8-26 
Unpack Signed Destructive, 8-26 
Unpack Signed Update, 8-26 

Valid Index, 3-4 

Value Call, 6-3 

Varient Mode Operation and Opera- 
tors , 8-1 

Visual Message Control Center, 4-34 

Word Data Descriptor, 6-^> 
Write IC Operation, 4-19 



nine 



INDEX (cont) 



Write IC Switch, 4-19 
Write Main Memory, 4-28 
Write SCM , 4-27 

X Register, 4-2 

Y Register, 4-2 



ten 



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